Stratix^® 10 SX

Q: When should I choose Stratix 10 SX SoC FPGA instead of GX?

Choose SX when integrated Arm Cortex-A53 processing is needed alongside FPGA logic. Compare the exact device's I/O and resource options.

Q: How does an SX developer choose 32-bit versus 64-bit software execution?

Select a supported OS/toolchain mode according to memory, application and library requirements, then validate the complete boot and runtime configuration.

Q: How does a designer manage shared buffers between the SX HPS and FPGA?

Use the documented interface and coherency behavior. Define ownership and apply required memory ordering and cache maintenance.

Q: How does an engineer troubleshoot an SX boot stall after changing FPGA peripherals?

Compare boot handoff, device tree, clocks, resets and bridge initialization with the new hardware. Check the first failing boot-stage log.

Q: When should SX hardware acceleration replace an Arm software routine?

Consider it when profiling shows a suitable bottleneck and parallel hardware benefit exceeds data-transfer and synchronization costs.

SoC FPGA

Highest-performance SoC FPGAs, integrating a quad-core 64-bit Arm Cortex-A53 processor with HyperFlex^® FPGA fabric.

Download Product Table

Explore the Stratix^® 10 SX SoC FPGA

Stratix 10 SX SoC FPGAs combines a quad-core Arm Cortex*-A53 MPCore hard processor system with the groundbreaking Hyperflex^® FPGA Architecture to deliver the performance, power efficiency, density, and integration required for embedded applications.

Key Features

Hard Processor System (HPS)	At the heart of the HPS is a highly efficient quad-core Arm Cortex-A53 processor cluster, and this processor is optimized for ultra-high performance per watt, which reduces power consumption. The HPS includes a System Memory Management Unit, Cache Coherency Unit, a hard memory controller, and a rich feature set of embedded peripherals.
Digital Signal Processing (DSP)	With Stratix 10 devices, DSP designs can achieve up to 8.6 Tera floating point operations per second (TFLOPS) of IEEE 754 single-precision floating-point operations.
Secure Device Manager (SDM)	SDM controls key operations, such as configuration, device security, single event upset (SEU) responses, and power management. It creates a unified, secure management system for the entire device, including the FPGA fabric, HPS in SoCs, embedded hard IP blocks, and I/O blocks.

Benefits

Enabling Designers to Do More with HPS While Balancing Power Efficiency

With an embedded HPS based on a quad-core Arm Cortex-A53 MPCore processor, Stratix 10 SX FPGAs deliver power-efficient, application-grade performance and enable designers to implement hardware-assisted virtualization directly in the FPGA fabric.

Achieve High Levels of System Integration

The Stratix 10 SX SoC FPGA empowers the USR in the Arm ecosystem. Arm's next-generation 64-bit architecture (ARMv8) enables hardware virtualization, system management and monitoring capabilities, and acceleration pre-processing. The Arm Cortex-A53 processor supports 32-bit execution mode and board support packages for popular operating systems, including Linux*, Wind River’s VxWorks*, Micrium’s uC/OS-II* and uC/OS-III*, and more.

Achieve High Designer Productivity with Optimized FPGA and SoC FPGA Software

Optimized for multi-million logic elements (LE), the Virtual Platform streamlines design iterations, fostering early software development. The SoC FPGA Embedded Development Suite (EDS) enables debugging, profiling and whole-chip visualization with the Arm Development Studio 5* (DS-5*) FPGA Edition Toolkit.

Ordering starts with a part number. Select a product in the table below to view its ordering part numbers (OPNs).

Part Number Decoder Compare All Products

Loading...

Start Design

Everything you need to begin a Stratix 10 SX SoC FPGA design.

Development Kits

Stratix 10 SX SoC Development Kit

Integrated Arm processing with FPGA fabric for embedded systems.

Find Partner Boards

IP & Example Designs

Interlaken IP

This pre-built, ready-to-go IP building block shortens the design cycle resulting in faster time to market.

Nios® V Processors

By leveraging the RISC-V instruction set architecture (ISA), the Nios V processors offer scalable solutions that enable a spectrum of applications ranging from simple embedded systems to complex, high-performance applications.

FPGA Developer Site

GitHub site that provides a single location for developers to find and use Altera example designs, software, drivers, and associated collateral.

FPGA Design Store

Jumpstart your project with the latest design examples targeting Quartus^®Prime Design Software v16.0 and above.

Software

Quartus Prime Design Software Pro Edition

Provides comprehensive FPGA design capabilities with broad device support and essential tools for design planning, compilation, and analysis.

Solutions

Stratix 10 SX SoC FPGAs for Industrial

Explore Industrial Solutions

Resources

Start developing with Stratix 10 SX SoC FPGAs with these resources.

Stratix 10 SX SoC FPGA Product Table

Stratix 10 SX FPGA Device Overview

Stratix 10 FPGA Datasheet

View All Documentation

Common Questions

When should I choose Stratix 10 SX SoC FPGA instead of GX?

How does an SX developer choose 32-bit versus 64-bit software execution?

How does a designer manage shared buffers between the SX HPS and FPGA?

How does an engineer troubleshoot an SX boot stall after changing FPGA peripherals?

When should SX hardware acceleration replace an Arm software routine?

Ready to Order?

Ordering starts with a part number. Select a product in the table above to view its OPNs — which encode density, speed grade, package, and options — then use that OPN to check availability and purchase through an authorized distributor. Refer to Parts Decoder to decode a OPN.

Contact a Distributor Talk to a Sales Rep