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Mid-Range
Arria® V FPGA and SoC FPGA
Arria V FPGAs deliver high bandwidth, low power consumption, and flexible integration for midrange communications and broadcast applications.
Explore Arria V Family
The Arria V FPGA family offers the highest bandwidth and delivers the lowest total power for midrange applications, such as remote radio units, 10G/40G line cards, and broadcast studio equipment. There are five targeted variants, including SoC variants with a dual-core ARM* Cortex*-A9 hard processor system (HPS) to best meet your performance, power, and integration needs.
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Arria V GZ FPGA
Offers the lowest power-per-bandwidth for midrange applications, and are ideal for power-sensitive designs that require transceivers up to 12.5 Gbps.
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Arria V GT FPGA
Offers the lowest total power for mid-range applications and the lowest power transceivers for speeds up to 10.3125 Gbps.
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Arria V GX FPGA
Offers the lowest total power for mid-range applications and the lowest power transceivers for speeds up to 10.3125 Gbps.
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Arria V ST SoC FPGA
Altera SoC FPGA with ARM*-based HPS and 10.3125 Gbps transceivers.
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Arria V SX SoC FPGA
Altera SoC FPGA with ARM*-based HPS and 6.5536 Gbps backplane-capable transceivers.
Start Design
Choose a resource below to start your MAX V CPLD design, from development kit to software downloads.
FFT FPGA IP Cores
The Fast Fourier transform (FFT) FPGA intellectual property (IP) core is a high-performance, highly parameterizable FFT processor.
Nios® V Processors
By leveraging the RISC-V instruction set architecture (ISA), the Nios V processors offer scalable solutions that enable a spectrum of applications ranging from simple embedded systems to complex, high-performance applications.
FPGA Developer Site
GitHub site that provides a single location for developers to find and use Altera example designs, software, drivers, and associated collateral.
FPGA Design Store
Jumpstart your project with the latest design examples targeting Quartus® Prime Design Software v16.0 and above.
Quartus Prime Design Software Standard Edition
Provides comprehensive FPGA design capabilities with broad device support and essential tools for design planning, compilation, and analysis.
Quartus Prime Design Software Lite Edition
A free, entry-level FPGA design solution that provides basic compilation, programming, and debugging capabilities for select device families.
Resources
Training & Learning
Common Questions
Select GX, GT or GZ according to documented serial-rate requirements, then compare logic, memory and package resources.
SX and ST include an Arm HPS alongside FPGA fabric. GX, GT and GZ are FPGA options without that hard processor.
Use the device overview: GX is specified up to 6.5536 Gbps and GT up to 10.3125 Gbps.
Evaluate migration when required performance, interfaces or maintainability exceed the existing design. Confirm availability separately rather than inferring lifecycle status.
Archive the supported Quartus Standard release, IP, constraints and scripts, then verify rebuild results before hardware changes.