Mid-Range
Arria® 10 FPGAs and SoC FPGAs
Arria 10 FPGAs and SoC FPGAs deliver high performance, power efficiency, and flexibility for a wide range of midrange applications.
Explore Arria 10 Family
Arria 10 FPGAs and SoC FPGAs deliver more than a full speed grade of core performance improvement and up to a 20% advantage in fMAX compared to the competition, based on publicly available OpenCore designs. They also offer up to 40% lower power consumption than previous-generation FPGAs and SoC FPGAs. With their combination of performance, power efficiency, and compact form factor, Arria 10 devices are ideal for a broad range of applications, including communications, data center, military, broadcast, automotive, and other midrange FPGA use cases.
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Arria 10 GT FPGA
Enabled with up to 78 full-duplex transceivers with data rates up to 25.78 Gbps chip-to-chip.
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Arria 10 GX FPGA
Enabled with up to 96 full-duplex transceivers with data rates up to 17.4 Gbps chip-to-chip.
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Arria 10 SX SoC FPGA
Enabled with a dual-core ARM* Cortex*-A9 HPS, up to 48 full-duplex transceivers.
Start Design
Choose a resource below to start your MAX V CPLD design, from development kit to software downloads.
FFT FPGA IP Cores
The Fast Fourier transform (FFT) FPGA intellectual property (IP) core is a high-performance, highly parameterizable FFT processor.
Nios® V Processors
By leveraging the RISC-V instruction set architecture (ISA), the Nios V processors offer scalable solutions that enable a spectrum of applications ranging from simple embedded systems to complex, high-performance applications.
FPGA Developer Site
GitHub site that provides a single location for developers to find and use Altera example designs, software, drivers, and associated collateral.
FPGA Design Store
Jumpstart your project with the latest design examples targeting Quartus® Prime Design Software v16.0 and above.
Quartus Prime Design Software Standard Edition
Provides comprehensive FPGA design capabilities with broad device support and essential tools for design planning, compilation, and analysis.
Quartus Prime Design Software Lite Edition
A free, entry-level FPGA design solution that provides basic compilation, programming, and debugging capabilities for select device families.
Resources
Start developing with Arria 10 Family.
Training & Learning
Common Questions
Choose GT for its higher serial rate, GX for its resource/connectivity balance, and SX when an integrated Arm HPS is required.
Compare actual workload resources, memory, I/O, power and software needs. Neither family is a drop-in replacement for the other.
Different channels have different loss and integrity requirements. Use the specified rate for the intended channel type and device grade.
Choose a supported edition based on required flow, IP compatibility and validated release. Both editions list Arria 10 support.
Match density, package, speed/temperature grade and interfaces to the design, then confirm availability with an authorized distributor.