Arria® 10 SX SoC FPGA Overview

At 20nm, Arria 10 SX SoC FPGAs feature a dual-core ARM Cortex-A9 HPS, support up to 48 full-duplex transceivers with data rates up to 17.4 Gbps chip-to-chip and 12.5 Gbps backplane communications, while providing up to 660K equivalent logic elements.

Arria 10 SX FPGA Product Table

Benefits

Integrated Processing and Programmable Logic

Combines FPGA fabric with integrated dual-core ARM® Cortex®-A9 processors, enabling hardware-software co-design for embedded applications that require both programmable logic and software programmability.

Flexible Embedded System Integration

Simplifies system integration by consolidating processing, I/O, and custom acceleration on a single device, reducing board complexity and improving design efficiency.

Power-Efficient Performance for Complex Designs

Provides flexibility for control-plane, data-plane, and system management functions, supporting a variety of embedded applications such as industrial automation, automotive, and communications systems.

Key Features

Enhanced ARM Processor

Dual-core ARM* Cortex-A9* MPCore* processor with ARM* CoreSight* debug and trace technology. At 1.5 GHz, the processor provides increased performance and reduced power.

Improved SoC Architecture

With three Ethernet MAC cores, 256 KB Scratch-RAM, supports 8-and 16-bit NAND flash devices, embedded MultiMediaCard (eMMC) SD/SDIO/MMC cards, and 72-bit DDR3/4 memory for building an improved architecture.

Enhanced Security

This SoC FPGA supports secure boot with Elliptical Curve Digital Signature Authentication (EC DSA) authentication, with a layered public key infrastructure for root of trust support, Advanced Encryption Standard (AES), and new anti-tamper features.

Applications

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Get Started: Development Kits, IP, Example Designs and Software

Arria 10 SX SoC Development Kit

ARM-embedded platform for hardware-software co-design.

Explore more board offerings

eCPRI FPGA IP

The enhanced Common Public Radio Interface (eCPRI) Altera® FPGA IP core implements the eCPRI specification version 2.0. It is a front-haul interface protocol for radio base stations aimed at connecting the eCPRI Radio Equipment Control (eREC) and the eCPRI Radio Equipment (eRE) via front-haul transport network.