Cyclone® 10 LP FPGA Overview

The Cyclone® 10 LP FPGA extends the Cyclone FPGA series leadership in low-power devices targeted for high-volume and cost-sensitive applications.

Cyclone® 10 LP FPGA Product Table

Benefits

Half the Power at Half the Cost

Ideal for high-volume, cost-sensitive functions, the Cyclone 10 LP FPGA is designed for a broad spectrum and suits smart and connected end applications across many market segments.

Lower Your System Costs

All Cyclone 10 LP FPGAs require only two core power supplies for operation, simplifying your power distribution network and saving you board costs, board space, and design time. This enables you to design a lower cost system.

Reduce Power Consumption

Built on a power-optimized 60 nm process, the Cyclone 10 LP FPGA extends the low-power leadership of the previous-generation Cyclone V FPGA. The latest generation devices reduce core static power by up to 50 percent compared with the previous generations.

Key Features

Embedded Multipliers

Each embedded multiplier block in the devices supports one individual 18 × 18-bit multiplier or two individual 9 × 9-bit multipliers. Cascade multiplier blocks to form wider or deeper logic structures.

Logic Elements and Logic Array Blocks

The logic array block (LAB) consists of 16 logic elements (LEs), each with four inputs, a four-input look-up table (LUT), a register, and output logic. The four-input LUT is a function generator that can implement any function with four variables.

Embedded Memory Blocks

The embedded memory structure consists of M9K memory blocks columns. Each M9K memory block of on the device provides 9 Kb of on-chip memory.

Single Event Upset (SEU)

The cyclic redundancy check (CRC) error detection feature can check for an SEU continuously, automatically confirming the accuracy of the configuration data stored in the device and alerting the system to an occurrence of a configuration error.