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Power and Cost-Optimized FPGA and SoC FPGA
Agilex® 3
Bringing high performance to the power and cost-optimized space, with compact form factors, AI tensor blocks and dual Arm Cortex-A55 cores.
Optimized for Cost-Effective and Space-Efficient Designs
Agilex 3 brings the Hyperflex FPGA architecture to power and cost-optimized applications. AI-optimized DSPs with tensor blocks, hardened IP, dual Arm Cortex-A55 cores, and 12.5 Gbps transceivers fit into compact variable pitch BGA packages that maintain low-cost PCB design rules.
Up to
1.9X
Higher fabric performance
Up to
38%
Lower total power
Up to
12.5
Gbps Transceivers
Benefits
Upgraded Performance
Agilex 3 brings the high-performance Hyperflex FPGA architecture to power and cost-optimized applications. 12.5 Gbps transceivers, advanced LPDDR5 memory support, 1.25 Gbps LVDS, and 2.5G MIPI D-PHY improve system bandwidth and reduce data bottlenecks getting data into and out of the FPGA.
Higher Integration
AI-optimized DSPs with tensor blocks and hardened IP blocks deliver robust capability in a single chip alongside dual Arm Cortex-A55 cores. Variable pitch BGA packaging enables higher IO density while maintaining low-cost manufacturing PCB design rules.
Security and Reliability
The Secure Device Manager offers advanced security features including post-quantum cryptography secure boot, bitstream encryption and authentication, physically unclonable function key storage, and physical anti-tamper protection.
Specifications
Enhanced DSP with AI Tensor Block
Offers up to 3.6 peak INT8 TOPS, with FPGA AI Suite support enabling a push-button flow from industry-standard frameworks to FPGA bitstream.
Transceivers and Hard IP
The GTS transceiver supports data rates up to 12.5 Gbps and integrates hard IP for PCIe 3.0 x4 and 10GbE, reducing design time and on-chip resource use.
Secure Device Manager
Provides secure boot, AES encryption, and FPGA configuration management, with runtime sensors and tamper detection for authenticated configuration, bitstream encryption, and protection against unauthorized access.
Dual-Core Arm Cortex-A55 SoC
Selected SoC devices integrate a hardened dual-Core Arm Cortex-A55 SoC processor system for control-plane software, embedded processing, and tightly coupled hardware acceleration.
LVDS and MIPI D-PHY Interfaces
1.25 Gbps LVDS and 2.5G MIPI D-PHY support sensor, camera, and display interfacing for embedded vision and panel-driving designs.
Second-Generation Hyperflex™ FPGA Architecture
Hyper-Registers distributed throughout the fabric bring high-performance architecture to the cost-optimized tier, supporting higher clock frequencies within a small power budget.
Variable Pitch BGA Packaging
Variable pitch BGA packaging increases ball count within the same footprint as traditional packages while keeping standard PCB design rules, so board cost does not rise with device capability.
Product Package & Combination Selector
Start Design
Start an Agilex 3 design with the C-Series development kit, production design software, hardened Ethernet and memory IP, example designs, and guided design journeys for architecture, board, interface, application, AI, and software development.
Agilex 3 FPGA and SoC C-Series Development Kit
A compact, power-efficient platform for embedded and edge development, with PCIe 3.0, DisplayPort 1.4, dual MIPI, dual LPDDR4 banks, onboard USB-Blaster III, and expansion headers for Raspberry Pi HATs and Pmod modules.
View All Agilex 3 Boards
Browse Altera and partner boards for Agilex 3 devices when the reference kit does not match the target form factor.
GTS Ethernet Hard IP
Supports 10GE on Agilex 3 devices using hardened MAC, PCS, and FEC, reducing design time and on-chip resource use.
LPDDR4/5/5x External Memory Interface IP
Supports high-speed memory access for balanced workloads through hardened external memory controllers.
Example Designs
Find example designs, documentation, and software tools that shorten bring-up and reduce time to production.
Quartus Prime Pro Edition Design Software
Compile, place and route, verify timing, and program Agilex 3 FPGA and SoC designs
FPGA AI Suite
Build and deploy AI inference pipelines that use the Enhanced DSP with AI Tensor Block, with a push-button flow from industry-standard frameworks to bitstream.
Ashling RISCFree IDE
Develop and debug software for the Arm Cortex-A55 processor system and Nios V soft processors in Agilex 3 SoC designs.
Solutions
Integrate real-time control, machine vision, robotics, and networking on one compact device, with hardened Ethernet, deterministic processing, and an Arm processor system for embedded control.
Process imaging and sensor data at the point of care with MIPI and LVDS interfacing, low power, and long product lifecycles suited to regulated equipment.
Bridge interfaces, drive displays, and add edge intelligence in high-volume products where board area and unit cost decide the design.
Protect designs and data with post-quantum cryptography secure boot, bitstream authentication, PUF key storage, and physical anti-tamper protection.
Drive high-resolution displays and LED walls with MIPI and DisplayPort interfacing, parallel processing, and adaptable format support.
Add inference to compact, power-constrained products using AI tensor blocks delivering up to 3.6 peak INT8 TOPS and a push-button flow from standard frameworks.
Support in-vehicle networking, sensor interfacing, and display systems with a small footprint and hardened connectivity.
Resources
Documentation, downloads, videos, training, and support for Agilex 3.
Documentation
Support and Community
Common Questions
Choose Agilex 3 when its logic, I/O and processing resources meet requirements at the desired cost and footprint. Compare specific devices.
SoC options include a hard processor system. Confirm processor availability and peripheral resources for the exact ordering part.
It can help meet PCB manufacturing goals, but routing and layer count depend on the selected package, escape strategy and interfaces.
Use supported-model compilation and resource estimates, then validate latency and accuracy. Peak tensor-block performance is not application throughput.
Check the selected part's security flow, keys, image authentication and configuration status using the relevant SDM documentation.
Programmable logic, processor options and high-speed interfaces can combine sensor handling and control. Check the required protocol and package support.
Ready to Order
Confirm the device, logic density, package, speed grade, temperature range, SoC option, and lifecycle requirements in the current product table. Then contact an authorized distributor or an Altera representative for availability and purchasing support.