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Agilex® 3 FPGA Interface Protocol Design Journey

Interactive step-by-step guidance of FPGA Resources and Documentation for Interface Protocols.

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Ethernet Interface

Transceiver and IO Design

PCIe Interface

Memory and Flash

Embedded Peripherals

Video Interfaces

Wireless Interfaces

Discover Ethernet IP Portfolio Design Considerations Design with Ethernet MAC Interfaces Add 10G MAC Interface Add Triple Speed Ethernet MAC Interface Design with Ethernet PHY Interfaces Add Multi-Rate 10G Ethernet PHY Design with Ethernet Precision Time Protocols Precision Time Protocol (PTP) 1588 Solutions
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Please select the desired journey step from the flowchart to view the applicable assets.

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Please select the desired Discover Ethernet IP Portfolio sub-step from the flowchart to the left to view the applicable assets:

  • Design Considerations
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Please select the desired Design with Ethernet MAC Interfaces sub-step from the flowchart to the left to view the applicable assets:

  • Add 10G MAC Interface
  • Add Triple Speed Ethernet MAC Interface
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Please select the desired Design with Ethernet PHY Interfaces sub-step from the flowchart to the left to view the applicable assets:

  • Add Multi-Rate 10G Ethernet PHY
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Please select the desired Design with Ethernet Precision Time Protocols sub-step from the flowchart to the left to view the applicable assets:

  • Precision Time Protocol (PTP) 1588 Solutions
Overview
infoAltera® FPGA IP for Ethernet Products Portfolio
infoEthernet Getting Started Video
infoEthernet IP - Support Center
articleGTS Ethernet Hard IP Training
Overview
infoGTS Ethernet Hard IP Overview
infoLow Latency Ethernet 10G MAC IP Overview
picture_as_pdfGTS Ethernet Hard IP Release Notes
picture_as_pdfGTS Auto-Negotiation and Link Training for Ethernet IP Release Notes
picture_as_pdfLow Latency Ethernet 10G MAC IP Release Notes
Design
picture_as_pdfGTS Ethernet Hard IP User Guide
picture_as_pdfLow Latency Ethernet 10G MAC IP User Guide
picture_as_pdfLow Latency Ethernet 10G MAC IP Design Example User Guide
articleGTS Ethernet FPGA Hard IP Register Map
articleGTS Auto-Negotiation and Link Training IP Register Map
Debug
picture_as_pdfEthernet Toolkit User Guide
listKnowledge Base Solution for Altera® FPGA IPs
Overview
infoTriple-Speed Ethernet IP Overview
picture_as_pdfTriple-Speed Ethernet IP Release Notes
Design
picture_as_pdfTriple-Speed Ethernet IP User Guide
picture_as_pdfTriple-Speed Ethernet IP Design Example User Guide
picture_as_pdfGMII to RGMII Converter Core (Embedded Peripherals User Guide)
Debug
listKnowledge Base Solution for Altera® FPGA IPs
Overview
info1G/2.5G/5G/10G Multirate Ethernet PHY IP Overview
picture_as_pdf1G/2.5G/5G/10G Multirate Ethernet PHY IP Release Notes
picture_as_pdfGTS Dynamic Reconfiguration Controller Release Notes
Design
picture_as_pdf1G/2.5G/5G/10G Multirate Ethernet PHY IP User Guide
picture_as_pdfGTS Dynamic Reconfiguration Controller IP User Guide: Agilex™ 3 FPGAs and SoCs
Debug
listKnowledge Base Solution for Altera® FPGA IPs
Design
picture_as_pdfEthernet Design Example Components Release Notes
picture_as_pdfEthernet Design Example Components User Guide
Debug
listKnowledge Base Solution for Altera® FPGA IPs
Design With IO Design with GPIO and LVDS IO Design With Transceiver Design with GTS Transceiver
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Please select the desired journey step from the flowchart to view the applicable assets.

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Please select the desired Design With IO sub-step from the flowchart to the left to view the applicable assets:

  • Design with GPIO and LVDS IO
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Please select the desired Design With Transceiver sub-step from the flowchart to the left to view the applicable assets:

  • Design with GTS Transceiver
Overview
picture_as_pdfGPIO IP Release Notes
picture_as_pdfLVDS SERDES IP Release Notes
picture_as_pdfIOPLL FPGA IP Release Notes
Design
picture_as_pdfGeneral-Purpose I/O User Guide
picture_as_pdfLVDS SERDES User Guide
Overview
picture_as_pdfDevice Design Guidelines
infoGTS Transceiver Basics Training
picture_as_pdfGTS PMA/FEC Direct PHY IP Release Notes
infoTransceiver PHY IP - Support Center
Plan
infoIBIS Models for Altera® FPGA Devices
Design
articleGTS Transceiver Clocking and Datapath Tool
articleGTS PMA/FEC Direct PHY IP Register Map
picture_as_pdfGTS Transceiver PHY User Guide
Debug
articleGTS Transceiver TX Equalizer Tool
picture_as_pdfGTS Transceiver Toolkit
listKnowledge Base Solution for Altera® FPGA IPs
Design with PCI Express (PCIe) IP Discover PCIe IP Solutions Add PCIe Gen 3 Interface
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Please select the desired journey step from the flowchart to view the applicable assets.

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Please select the desired Design with PCI Express (PCIe) IP sub-step from the flowchart to the left to view the applicable assets:

  • Discover PCIe IP Solutions
  • Add PCIe Gen 3 Interface
Overview
infoPCIe* FPGA IP
infoPCI* Express IP Support Center
listAltera® FPGA PCNs, PDNs, and ADVs
articleGTS PCI Express* Hard IP Training
Overview
infoGTS AXI Streaming FPGA IP for PCI Express* Overview
infoMultichannel DMA IP for PCI Express* Overview
picture_as_pdfGTS AXI Streaming IP for PCI Express* Release Notes
picture_as_pdfGTS AXI Multichannel DMA IP for PCI Express* Release Notes
Design
picture_as_pdfGTS AXI Streaming IP for PCI Express* User Guide
picture_as_pdfGTS AXI Streaming IP for PCI Express* Design Example User Guide
articleGTS AXI Streaming IP for PCI Express* Register Map
picture_as_pdfGTS AXI Multichannel DMA IP for PCI Express User Guide
picture_as_pdfMSI to GIC Generator Core Overview
Training
articleUsing GTS AXI Streaming IP for PCI Express*
Debug
listKnowledge Base Solution for Altera® FPGA IPs
Add DDR Memory Interfaces Add LPDDR4 Memory Interface Add Flash Memory Interfaces Add QSPI Flash Interface Add NAND Flash Interface Add SD/MMC Flash Interface Add On-Chip Memory Add On-Chip Memory Add DMA Controller Add Modular Scatter-Gather DMA Core Add HPS DMA Controller
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Please select the desired journey step from the flowchart to view the applicable assets.

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Please select the desired Add DDR Memory Interfaces sub-step from the flowchart to the left to view the applicable assets:

  • Add LPDDR4 Memory Interface
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Please select the desired Add Flash Memory Interfaces sub-step from the flowchart to the left to view the applicable assets:

  • Add QSPI Flash Interface
  • Add NAND Flash Interface
  • Add SD/MMC Flash Interface
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Please select the desired Add On-Chip Memory sub-step from the flowchart to the left to view the applicable assets:

  • Add On-Chip Memory
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Please select the desired Add DMA Controller sub-step from the flowchart to the left to view the applicable assets:

  • Add Modular Scatter-Gather DMA Core
  • Add HPS DMA Controller
Overview
picture_as_pdfEMIF FPGA IP Core Release Notes
picture_as_pdfTest Engine FPGA IP Release Notes
picture_as_pdfPerformance Monitor FPGA IP Release Notes
infoExternal Memory Interfaces IP - Support Center
listAltera® FPGA PCNs, PDNs, and ADVs
Training
articleIntroduction to Memory Interfaces
articleUsing Memory Interfaces
articleIntegration of Memory Interfaces
articleVerifying Memory Interfaces
articleFast and Easy I/O System Design with Interface Planner
articleEMIF Debug Toolkit
EMIF Device Selection
infoEMIF Spec Estimator Tool
articleEMIF Spec Estimator Tool Tutorial
Design
picture_as_pdfEMIF IP User Guide
picture_as_pdfTest Engine FPGA IP User Guide
picture_as_pdfPerformance Monitor FPGA IP User Guide
Debug
listKnowledge Base Solution for Altera® FPGA IPs
Overview
infoDevice Configuration - Support Center
Design
picture_as_pdfMailbox Client Altera® FPGA IP User Guide
picture_as_pdfGeneric Serial Flash Interface FPGA IP User Guide
picture_as_pdfHPS Use of SDM QSPI Controller
picture_as_pdfFlash Access Migration Guidelines from Control Block-Based Devices to SDM-Based Devices
Get Device Driver
picture_as_pdfHAL Driver - Generic Serial Flash Interface IP Overview
picture_as_pdfHAL Driver - Mailbox Client IP Overview
Overview
picture_as_pdfHPS NAND Flash Controller
Overview
picture_as_pdfHPS SD/eMMC Host Controller
Design
picture_as_pdfOn-Chip Memory II (RAM or ROM) Altera® FPGA IP
Design
picture_as_pdfModular Scatter-Gather DMA Core
Get Device Driver
picture_as_pdfHAL Driver - Modular Scatter-Gather DMA Core Overview
Overview
picture_as_pdfHPS DMA Controller
Before You Begin Discover Embedded Peripheral IP Portfolio Design with General Purpose IO Add General Purpose IO Soft IP Add HPS GPIO Interface Design with UART Interface Add UART Soft IP Interface Add JTAG UART Interface Add HPS UART Controller Design with JTAG Interface Add JTAG Interface Design with I2C Interface Add I2C Soft IP Interface Add HPS I2C Controller Design with I3C Interface Add HPS I3C Controller Design with SPI Interface Add SPI Interface Add eSPI Interface Add HPS SPI Controller Design with USB Interface Add HPS USB 2.0 OTG Controller Add HPS USB 3.1 Gen1 Controller Design with HPS Interface Add Cache Coherency Translator
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Please select the desired journey step from the flowchart to view the applicable assets.

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Please select the desired Before You Begin sub-step from the flowchart to the left to view the applicable assets:

  • Discover Embedded Peripheral IP Portfolio
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Please select the desired Design with General Purpose IO sub-step from the flowchart to the left to view the applicable assets:

  • Add General Purpose IO Soft IP
  • Add HPS GPIO Interface
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Please select the desired Design with UART Interface sub-step from the flowchart to the left to view the applicable assets:

  • Add UART Soft IP Interface
  • Add JTAG UART Interface
  • Add HPS UART Controller
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Please select the desired Design with JTAG Interface sub-step from the flowchart to the left to view the applicable assets:

  • Add JTAG Interface
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Please select the desired Design with I2C Interface sub-step from the flowchart to the left to view the applicable assets:

  • Add I2C Soft IP Interface
  • Add HPS I2C Controller
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Please select the desired Design with I3C Interface sub-step from the flowchart to the left to view the applicable assets:

  • Add HPS I3C Controller
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Please select the desired Design with SPI Interface sub-step from the flowchart to the left to view the applicable assets:

  • Add SPI Interface
  • Add eSPI Interface
  • Add HPS SPI Controller
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Please select the desired Design with USB Interface sub-step from the flowchart to the left to view the applicable assets:

  • Add HPS USB 2.0 OTG Controller
  • Add HPS USB 3.1 Gen1 Controller
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Please select the desired Design with HPS Interface sub-step from the flowchart to the left to view the applicable assets:

  • Add Cache Coherency Translator
Overview
picture_as_pdfEmbedded Peripherals IP User Guide
picture_as_pdfTool Support
picture_as_pdfDevice Support
Overview
picture_as_pdfPIO Core Overview
picture_as_pdfGPIO FPGA IP Release Notes
picture_as_pdfGeneral-Purpose I/O User Guide
Overview
picture_as_pdfHPS General-Purpose I/O Interface (GPIO)
Overview
picture_as_pdf16550 Compatible UART Core Overview
picture_as_pdfLightweight UART Core Overview
Drivers
picture_as_pdfHAL Driver - 16550 Compatible UART Core Overview
picture_as_pdfHAL Driver - Lightweight UART Core Overview
Overview
picture_as_pdfJTAG UART Core Overview
Drivers
picture_as_pdfHAL Driver - JTAG UART Core Overview
Overview
picture_as_pdfHPS UART Controller
Overview
picture_as_pdfJTAG to Avalon® Host Bridge Cores Overview
Overview
picture_as_pdfAvalon® I2C (Host) Core Overview
picture_as_pdfI2C Agent to Avalon® - MM Host Bridge Core
Drivers
picture_as_pdfHAL Driver - Avalon® I2C (Host) Core
articleLinux Driver - Avalon® I2C (Host) Core
Overview
picture_as_pdfHPS I2C Controller
Overview
picture_as_pdfHPS I3C Controller
Overview
picture_as_pdfSPI Core
picture_as_pdfAvalon®-ST Serial Peripheral Interface Core Overview
picture_as_pdfSPI Agent to Avalon® Host Bridge Cores
Drivers
picture_as_pdfHAL Driver - SPI Core Overview
articleLinux Driver - SPI Core
Overview
picture_as_pdfeSPI Agent Core Overview
Overview
picture_as_pdfHPS SPI Controller
Overview
picture_as_pdfHPS USB 2.0 OTG Controller
Overview
picture_as_pdfHPS USB 3.1 Gen1 Controller
Overview
picture_as_pdfAltera ACE5-Lite Cache Coherency Translator FPGA IP
Design with Video Interfaces Add MIPI Interface Add DisplayPort Interface Add SDI Interface Add HDMI Interface Design with Video and Vision Processing Suite Add Video and Vision Processing Suite
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Please select the desired journey step from the flowchart to view the applicable assets.

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Please select the desired Design with Video Interfaces sub-step from the flowchart to the left to view the applicable assets:

  • Add MIPI Interface
  • Add DisplayPort Interface
  • Add SDI Interface
  • Add HDMI Interface
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Please select the desired Design with Video and Vision Processing Suite sub-step from the flowchart to the left to view the applicable assets:

  • Add Video and Vision Processing Suite
Design
picture_as_pdfMIPI CSI-2 FPGA IP User Guide
picture_as_pdfMIPI D-PHY IP User Guide
picture_as_pdfMIPI DSI-2 IP User Guide
picture_as_pdfMIPI D-PHY IP Release Notes Agilex™ 3 and Agilex™ 5 FPGAs
Training
articleImplementing MIPI Solutions in Altera® FPGAs
Overview
infoDisplayPort IP Support Center
Design
picture_as_pdfDisplayPort FPGA IP User Guide
picture_as_pdfGTS DisplayPort FPGA IP Design Example User Guide
Debug
listKnowledge Base Solution for Altera® FPGA IPs
Overview
picture_as_pdfSerial Digital Interface (SDI) II FPGA IP Release Notes
infoSerial Digital Interface II IP Support Center
Design
picture_as_pdfGTS SDI II FPGA IP User Guide
picture_as_pdfGTS SDI II FPGA IP Design Example User Guide
picture_as_pdfSDI Audio FPGA IP User Guide
Debug
listKnowledge Base Solution for Altera® FPGA IPs
Design
picture_as_pdfGTS HDMI FPGA IP User Guide
picture_as_pdfGTS HDMI FPGA IP Design Example User Guide
Debug
listKnowledge Base Solution for Altera® FPGA IPs
Design
picture_as_pdfVideo and Vision Processing Suite FPGA IP User Guide
picture_as_pdfAltera® FPGA Streaming Video Protocol Specification
Design with ADC/DAC Data Converter Interfaces Add JESD204B Interface
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Please select the desired journey step from the flowchart to view the applicable assets.

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Please select the desired Design with ADC/DAC Data Converter Interfaces sub-step from the flowchart to the left to view the applicable assets:

  • Add JESD204B Interface
Overview
infoJESD204B FPGA IP Overview
picture_as_pdfGTS JESD204B IP Release Notes
infoJESD204B/JESD204C IP - Support Center
Design
picture_as_pdfGTS JESD204B IP User Guide
picture_as_pdfGTS JESD204B IP Design Example User Guide
Debug
listKnowledge Base Solution for Altera® FPGA IPs
Related Links
  • Agilex 3 FPGA Application Design Guided Journey
  • Agilex 3 System Architecture Guided Journey
  • Agilex 3 FPGA Board Design Guided Journey
  • Agilex 3 Software Development Guided Journey
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