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The FPGA Software Resources linked on the page are divided into functional areas according to the FPGA design flow.
| Agilex® FPGA and SoC FPGA Design Hubs | Description |
|---|---|
| Agilex® 7 FPGA and SoC FPGA | The Agilex® 7 FPGA resources are organized around a set of standard design processes that walk through the design steps to develop an FPGA-based platform. |
| Agilex® 5 FPGA and SoC FPGA | The Agilex® 5 FPGA resources are organized around a set of standard design processes that walk through the design steps to develop an FPGA-based platform. |
| Agilex® 3 FPGA and SoC FPGA | The Agilex® 3 FPGA resources are organized around a set of standard design processes that walk through the design steps to develop an FPGA-based platform. |
| FPGA Design Tools Resources | Description |
| FPGA Device and Product Support Collections | FPGA devices and product collections categorized by product lifecycle stages. |
| Questa*-Intel® FPGA Edition and ModelSim*-Intel® FPGA Edition Software Support | Support resources to help you resolve your simulation issues. |
| Embedded Design Tools Resources | Description |
| SOPC Builder Support | SOPC Builder documentation, user guides, design examples, and knowledge articles. |
| FPGA Development Tools Documentation | This collection provides documentation for the Quartus® Prime Design Software and other FPGA Development Tools. |
| SoC FPGA Embedded Development Suite | Starting with the SoC EDS v20.3 Pro and v21.1 Standard, the components are released to GitHub and Rocketboards.org. Customers can download exactly what they require, upgraded versions with the latest features, bug fixes, and security patches. Components are released more frequently, enabling faster and better tracking of code changes. |
| Nios® V Processor Documentation | Nios® V processor is the next generation of soft processor for Altera® FPGAs based on the open-source RISC-V Instruction Set Architecture. This processor is available in the Quartus® Prime Pro Edition Software starting with version 21.3. |
| Nios® II Processors Documentation | Nios® II processor, the world's most versatile processor, according to Gartner Research, is the most widely used soft processor in the FPGA industry. The Nios® II processor delivers unprecedented flexibility for your cost-sensitive, real-time, safety-critical (DO-254), and applications processing needs. The Nios® II processor supports all Altera® FPGA and SoC families. |
| High-Level Design Tools | Description |
| High-Level Synthesis (HLS) Compiler Support | Find technical documentation, videos, and training courses for the HLS Compiler. |
| Digital Signal Processing (DSP) Support | The DSP documentation presents the design flow commonly used in the FPGA design community. |
| Power | Description |
| Early Power Estimators (EPE) and Power Analyzer | Provides Early Power Estimators, FPGA Power and Thermal Calculator, and the Power Analyzer to give you the ability to estimate power consumption. |
| Software Resources | Description |
| Operating System Support | OS support information for Quartus Prime Pro, Standard, and Lite Edition Software and Additional Software. |
| Cable and Adapter Drivers Information | Find driver information and references for our FPGA Download Cable, EthernetBlaster, USB-Blaster, ByteBlaster II, ByteBlasterMV, and MasterBlaster cables. |
| Quartus® Prime and Quartus® II Software Scripting Support | Provides resources that include comprehensive scripting support for command-line and tool command language (Tcl) script design flows. |
| I/O Management and Board Development Support Center | Provides Documentation, Training, and Tools for early I/O planning and sign-off. |
| Design Entry and Planning Resource Center | Provides guidelines on planning and structuring your design, as well as details about managing metastability in your design, and HDL coding styles that can have a significant effect on the quality of your design's results. |
| Synthesis and Netlist Viewers Resource Center | Provides documentation for advanced integrated synthesis and interfaces with other third-party synthesis tools. |
| Incremental Compilation Resource Center | Provides instructions for the incremental compilation feature that includes incremental design methodology for high-density FPGAs. |
| Optimization Support Resources | Provides instructions for design optimization to help improve performance to reduce resource usage, close timing, and reduce compilation times. |
| Timing Analyzer Resource Center | Provides links to resources to learn more about the ASIC-strength static timing analyzer that supports the industry-standard Synopsys® Design Constraints (SDC) format. |
| Quartus II Classic Timing Analyzer Resource Center | Provides documentation for the classic timing analyzer included in Quartus II software. |
| On-Chip Debugging Resource Center | Provides links to available documentation about on-chip debugging tools. The on-chip debugging tools allow real-time capture of internal nodes in your design to help you verify your design quickly without the use of external equipment. |
| EDA Tool Support Resource Center | The EDA ecosystem ensures that you have a complete design solution for designing, verifying, and integrating Altera® FPGAs into your systems. |
| Downloads and Licensing | Description |
| Software Licensing Questions and Answers | This page contains basic questions and answers about licensing the Quartus® Prime design software. |
| FPGA Software Download Center | Download Quartus® Prime Software, DSP Builder, Simulation Tools, HLS, SDKs, PAC S/W, and more. Select by Operating System, by FPGA Device Family or Platform, or by Version. |
| FPGA Licensing Support Center | Information on license types, getting a license file, setting up a license file, and resolving license-related issues. |
| FPGA Support Resources | Support collateral for our customers to self-help/triage issues and to find links to available resources. |