On-chip Debugging Resource Center

Quick Design Debugging Using SignalProbe (PDF)

This chapter of the Quartus® Prime Software Development Software Handbook describes the SignalProbe feature. This feature makes design verification more efficient by quickly routing internal signals to I/O pins without affecting the design.

Design Debugging Using the SignalTap II Embedded Logic Analyzer (PDF)

This chapter of the Quartus® Prime Software Development Software Handbook provides a description of the verification flow using the SignalTap II embedded logic analyzer. The SignalTap II embedded logic analyzer debugs an FPGA design by probing internal signals in the design while the design is running at full speed.

In-system Debugging Using External Logic Analyzers (PDF)

This chapter of the Quartus® Prime Software Development Software Handbook provides information about the logic analyzer interface feature. This feature connects a large set of internal device signals to a small number of output pins for debugging purposes and allows you to take advantage of advanced features in your external logic analyzer.

In-system Updating of Memory and Constants (PDF)

This chapter of the Quartus® Prime Software Development Software Handbook describes the in-system memory content editor. This feature provides read and write access to in-system FPGA memories and constants through the JTAG interface.

Design Debugging Using In-system Sources and Probes (PDF)

This chapter of the Quartus® Prime Software Development Software Handbook describes the in-system sources and probes feature. This feature sets up customized register chains to drive or sample any logic node in your design, providing an easy way to input simple virtual stimuli and capture the current value of instrumented nodes.

Transceiver Link Debugging Using the Quartus® Prime Software Software (PDF)

This chapter in Quartus® Prime Software handbook describes how to use the new transceiver toolkit introduced in the Quartus® Prime Software software v10.0 to verify the high-speed links of FPGA transceiver-based devices in your system. FPGA also provides design examples with this chapter to get you started with the transceiver toolkit.

sld_virtual_jtag Megafunction User’s Guide (PDF)

This reference manual describes the Virtual JTAG megafunction, also known as the sld_virtual_jtag megafunction. The sld_virtual_jtag megafunction makes it easy to use the JTAG port as a simple communications interface, allowing you to develop custom debugging solutions.

AN 323: Using SignalTap II Embedded Logic Analyzers in SOPC Builder Systems (PDF)
Design files

This application note describes how to use the SignalTap II logic analyzer to monitor signals located inside a system module generated by SOPC Builder.

Design files for AN 323: Using SignalTap II Embedded Logic Analyzers in SOPC Builder Systems.

AN 446: Debugging Nios^® II Systems with the SignalTap II Logic Analyzer (PDF)

This application note examines the use of the Nios II plug-in within the SignalTap II logic analyzer and presents the capabilities, configuration options, and use-modes for the plug-in.

Learn how to verify high-speed transceiver links on your board using the transceiver toolkit (introduced in Quartus® Prime Software v10.0) with this online training course.

This is 40-minute online course.