Stratix® 10 GX FPGAs

Stratix 10 GX FPGAs contain up to 10.2 million logic elements and feature 96 general-purpose transceivers across separate chiplets. With 2,666 Mbps DDR4 external memory interface performance, these devices are optimized for FPGA applications requiring maximum transceiver throughput, I/O bandwidth, and core fabric performance.

Stratix 10 GX FPGA Product Table

Benefits

High Clock Performance and Lower Power Consumption

Stratix 10 FPGAs and SoC FPGAs use the Hyperflex™ core architecture, delivering higher throughput, improved power efficiency, enhanced design functionality, and increased developer productivity over previous-generation devices.

Runs on the Hyperflex™ FPGA Architecture

The Hyperflex™ FPGA Architecture introduces bypassable Hyper-Registers throughout the FPGA fabric—on interconnect routing segments and at the inputs of all functional blocks. These Hyper-Registers enable three advanced techniques to optimize core performance: Hyper-Retiming reduces critical path delays; Hyper-Pipelining improves timing closure by minimizing routing congestion; and Hyper-Optimization enhances overall device performance by enabling more aggressive timing and resource utilization strategies.

Enabling Next-Generation Chiplets Using 3D System-in-Package Technology

The patented Embedded Multi-Die Interconnect Bridge (EMIB) technology provides high-density interconnect between heterogeneous dies in the same package. It enables in-package functionality that was previously too complex or cost-prohibitive to implement using traditional multi-die packaging methods.

Key Features

Hyperflex™ FPGA Architecture

The core architecture delivers many advantages: higher throughput, improved power efficiency, greater design functionality, increased designer productivity and incorporates bypassable hyper-registers.

Heterogeneous 3D SiP Transceiver Tiles

The transceivers are on the heterogeneous 3D System-in-Package (SiP) transceiver tiles, each containing 24 full-duplex transceiver channels offering solutions for connectivity needs and future flexibility and scalability needs as data rates, modulation schemes, and protocol IPs evolve.

Secure Device Manager (SDM)

SDM controls key operations, such as configuration, device security, single event upset (SEU) responses, and power management. It creates a unified, secure management system for the entire device, including the FPGA fabric, hard processor system (HPS) in SoCs, embedded hard IP blocks, and I/O blocks.