Stratix® 10 TX FPGA Overview

The Stratix® 10 TX FPGA meets these rigorous demands with the newly developed PAM4 technology, enabling up to 57.8 Gbps in up to 144 transceiver lanes, meeting bandwidth needs of 5GB communications, cloud computing, network functions virtualization, and optical transport networks.

Stratix® 10 TX FPGA Product Table

Benefits

Enabling the Future of Networking

Stratix® 10 TX devices deliver dual-mode modulation, 57.8 Gbps PAM4, and 28.9 Gbps NRZ, enabling early adoption of next-generation data infrastructure and backward compatibility. With transceivers PAM4 capabilities, build next-generation communication and networking infrastructure that supports 50GE, 100GE, 200GE, 400GE, and terabit applications, allowing larger data transmission capacity than binary modulation.

Ethernet Hard IP Solution

The devices deliver power savings and latency time to market with hard IP solutions for Ethernet. The following hard IP(s) are available with the Stratix® 10 TX: Deterministic latency support for Common Public Radio Interface (CPRI) PCS, Option to bypass MAC, PCS, FEC, OTN PCS Mode, and the following 10GBASE-R/CR/KR, 25GBASE-R/CR/KR, 100GBASE-R4/CR4/KR4, 100GBASE-R2/CR2/KR2 Forward Error Correction (FEC).

Power Management Delivering Increased Power Saving

The advanced 14 nm tri-gate process technology and Hyperflex™ core architecture enable Hyper-Folding, power gating, and optional power reduction techniques to reduce total power consumption compared to previous generation high-performance Stratix® V devices. The device also features low-power transceivers and includes several hard IP blocks that reduce logic resources while delivering power savings compared to soft implementations.

Key Features

Hyperflex Core Architecture with Hyper-Registers

At the heart of the HPS is a highly efficient quad-core ARM* Cortex*-A53 processor cluster, and this processor is optimized for ultra-high performance per watt, which reduces power consumption. The HPS includes a System Memory Management Unit, Cache Coherency Unit, a hard memory controller, and a rich feature set of embedded peripherals.

Transceivers

The device offers up to 144 total full-duplex transceiver channels providing continuous data rates from 1 Gbps to 28.9 Gbps in NRZ mode and 2 Gbps to 57.8 Gbps in PAM4 mode for chip-to-chip, chip-to-module, and backplane applications.

Hard Processor System (HPS)

HPS performs better with an integrated quad-core 64-bit Arm* Cortex* -A53 while enabling system-wide hardware virtualization capabilities by adding a system memory management unit on selected Stratix® 10 TX devices.