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Data Center
DPU & AI NIC
Programmable DPUs and AI NICs built on Altera FPGAs free host CPUs for applications and keep accelerators fed at line rate.
Accelerate data paths, adapt to new needs
Data center infrastructure is changing rapidly as AI scales. New protocols, congestion control schemes, and security requirements arrive faster than fixed-function ASICs can follow, and running them in software takes CPU cores away from applications.
FPGAs give you both: line-rate hardware pipelines and a data path you can reprogram in the field. Altera® Agilex® FPGAs hold high fabric performance above 90% utilization, so networking, security, and preprocessing can run as one inline service chain on a single device.
The Challenges, and Why FPGA
The Challenge
Data paths that keep changing
New networking, storage, and security needs change the data path. Fixed-function ASICs need a respin, and software cannot hold line rate.
Why FPGA
Line-rate hardware you can reprogram
Adapt network protocols, security functions, and custom data paths in the field without redesigning the hardware or slowing the data path.
The Challenge
Infrastructure tax on host CPUs
Every core spent on virtual switching, encryption, or storage protocols is a core that cannot run applications or be rented to tenants.
Why FPGA
Custom offload, not a fixed feature set
Run OVS, RoCEv2, inline security, and your own custom functions in FPGA logic, so more host cores go back to applications and tenants.
The Challenge
Idle accelerators, wasted spend
Congestion and tail latency anywhere in the AI network leave accelerators waiting on data, so costly compute sits unused.
Why FPGA
Deterministic latency at scale
Hardware pipelines hold consistent tail latency at line rate, even at high fabric utilization, so accelerators spend less time waiting.
Why Altera
Proven at hyperscale
Powering network, storage, and security infrastructure across leading cloud environments.
Performance that holds as designs evolve
Agilex FPGAs hold high fabric performance above 90% utilization, so designs grow without hitting a performance wall.
An ecosystem that speeds development
Altera partners bring proven IP, boards, and design expertise, so your team can focus on what sets your design apart.
Easier to program, open to build on
Program data paths in P4 with P4 Suite for FPGA, and extend open-source drivers and APIs with Open FPGA Stack.
Get Started
More Data Center Applications
Storage
Runs NVMe-oF, compression, and encryption in programmable hardware at line rate, with predictable tail latency.
Platform Management
Consolidates power sequencing, management, and hardware root of trust into one in-field upgradable FPGA.
AI Inference
Accelerates the compute- and memory-bound phases of inference and scales disaggregated inference clusters.
Common Questions
An FPGA AI NIC provides programmable network data-path functions for AI-related traffic. A complete DPU system can also include embedded processing, control software and infrastructure services; compare the board architecture and software scope rather than the labels alone.
Use RoCEv2 offload when compatible endpoints and network configuration support the cluster's low-overhead data transfers. Evaluate congestion handling, queue resources and application integration alongside raw link speed.
Queue-pair capacity limits the simultaneously maintained communication contexts and consumes implementation resources. Size it for connection count, traffic pattern and buffering, and verify the claimed capacity for the selected IP and device configuration.
Inspect congestion, retransmissions, queue occupancy and host registration or transfer behavior alongside NIC timing. Compare results at controlled loads and packet sizes to distinguish fixed offload latency from network and endpoint waiting.
Programmable inline security can enforce supported traffic policies and cryptographic functions in the data path. Verify isolation, key handling, rule updates and exception behavior for each tenant because reconfigurability alone does not establish secure separation.