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Solution Stack
Video Solutions Stack
Move from evaluation to production faster with video connectivity IP, processing IP, and reference designs for broadcast, industrial, medical, and edge AI systems.
Accelerating Innovators to Shape What’s Next in Video Solutions
The Altera® Video Solutions Stack is a comprehensive set of video and imaging technologies designed to accelerate the development of advanced vision systems. It combines video connectivity IP, image and video processing IP, reference designs, development kits, documentation, and partner solutions. Supporting applications across broadcast, industrial automation, robotics, medical imaging, and edge AI, the stack enables designers to build flexible, high-bandwidth FPGA video systems while simplifying integration and speeding the transition from evaluation to production.
The Challenges, and Why FPGA
The Challenge
Rising pixel rates
4K, 8K and multi-sensor capture push pixel rates beyond what fixed-function processors handle easily.
Why FPGA
Custom FPGA pipelines
Build the pipeline you need with configurable scaling, warp, tone mapping, 3D LUT and ISP IP from the Video and Vision Processing Suite.
The Challenge
Too many interfaces
Supporting HDMI, DisplayPort, SDI, ST 2110 and MIPI in one product adds silicon, cost and design time.
Why FPGA
One programmable platform
Altera and partner IP cover display, broadcast, AV-over-IP and camera interfaces, and you can update them as standards change.
The Challenge
AI in the video path
Sending live video to a separate processor for inference adds latency, power and integration effort.
Why FPGA
Video and AI on one device
Optimized video path to AI compute | Run video capture, ISP, and pre-processing on the FPGA, and deliver clean, low-latency frames to the GPU or processor that runs the AI model.
The Challenge
Slow path to production
Building a video system from scratch takes time and carries integration risk.
Why FPGA
Proven starting points
Start faster with reference designs, development kits from Agilex® 3 to Agilex 7 FPGAs, and partner solutions.
Why Altera
Comprehensive Video IP
Build complete video pipelines with connectivity, image processing, and compression IP from Altera and its partners.
Proven Reference Designs
Accelerate development with FPGA-optimized examples for 4K imaging, AI inference, and video transport.
Scalable Hardware Platforms
Choose from a broad FPGA portfolio and development kits to match your video system’s performance, power, and connectivity needs.
Specialized Partner Ecosystem
Simplify integration with partner expertise, boards, and solutions for cameras, displays, codecs, and AV over IP.
Get Started
Reference Designs
4Kp60 Multi-Sensor HDR Camera
Full 4K camera reference with ISP suite
4Kp30 Multi-Sensor Camera with AI Inference
4K video pipeline + AI inference
Holoscan Sensor Bridge MIPI to 10GbE
MIPI D-PHY/ MIPI CSI-2 connected to NVIDIA Holoscan Sensor Bridge IP and Altera's 10GbE
MEP100 ST2110 SmartNIC by Macnica
Partner solution: ST2110 SmartNIC for IP video transport
JPEG‑XS Reference Design by IntoPIX
Partner solution: JPEG‑XS low‑latency codec reference design
USB‑to‑DisplayPort Reference Design by SLS Corp
Partner solution: USB‑to‑DisplayPort bridge design
8K Warp / TMO / 3D-LUT Demo
8K geometric correction + tone mapping + color pipeline
Video Connectivity IP
Display & Video Interfaces
Camera & Sensor Interfaces
Video & Image Processing IP
Core Video & Image Processing
Synchronization & Security
Compression & Codecs
Development Kits
Agilex® 7
Agilex® 5
Agilex® 3
Cyclone® V
Common Questions
The stack combines processing and connectivity IP, reference designs, kits, documentation and partner resources. The processing suite supplies a subset of those functions; selecting it alone does not provide every camera interface or codec.
Use a reference pipeline when its board, formats and supported releases fit the evaluation goals. Assemble blocks separately when interfaces or algorithms differ, preserving validated timing, buffering and video-format assumptions during integration.
Calculate pixel throughput and bits per pixel, then count each memory read and write across processing stages. Include buffering and sustained controller efficiency; streaming blocks can reduce memory passes when the algorithm supports them.
Check support before selecting the device and board, then confirm the matching core, tile, tool release and generated example. SDI II and older SDI IP have different documentation and applicability, so a general SDI label is insufficient.
Measure command arrival times, sequence numbers, queue depth and FPGA control deadlines separately. Check host scheduling, networking and interface buffering before modifying an otherwise stable hardware control loop.