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Wireline
Gateway
FPGAs implement flexible, reconfigurable hardware acceleration for network gateways.
Adaptable Acceleration for Gateways
Altera FPGAs implement Gateway functions by providing flexible and reconfigurable hardware acceleration for various network functions, supporting high-speed data processing tailored to specific protocol requirements.
FPGA-based Gateway functions benefit from hard-IP protocol support such as Ethernet and PCIe, enabling seamless integration with existing network infrastructure, plus high channel-rate transceivers with capabilities up to 116 Gbps.
The Challenges, and Why FPGA
The Challenge
Diverse, Evolving Traffic
Gateways must handle diverse and evolving network traffic patterns.
Why FPGA
Reconfigurable Hardware Acceleration
Flexible, reconfigurable acceleration tailors to specific protocol requirements.
The Challenge
Legacy Infrastructure Integration
Gateways must integrate seamlessly with existing network infrastructure.
Why FPGA
Hard-IP Ethernet & PCIe
Hard-IP protocol support enables seamless integration with existing infrastructure.
The Challenge
High-Speed Data Transmission
Gateway functions need efficient, high-speed data transmission.
Why FPGA
High Channel-Rate Transceivers
Transceivers with capabilities up to 116 Gbps enable efficient transmission.
Why Altera
Reconfigurable Gateway Logic
Flexible hardware acceleration adapts to diverse network function requirements.
Hard-IP Protocol Support
Ethernet and PCIe hard-IP simplify integration with existing infrastructure.
116 Gbps Transceivers
High channel-rate transceivers support efficient high-speed data transmission.
Field-Upgradeable Gateways
Update gateway functions as protocols and traffic patterns evolve.
Get Started
More Wireline Applications
NFVi
FPGAs bring hardware acceleration to Network Functions Virtualization Infrastructure.
End-to-End Security
Line-rate Crypto including MACsec and IPsec, plus post-quantum support on Agilex® FPGAs, from access to core, with security you can update in the field.
Routing/Switching Overlay
FPGAs power high-speed routing and switching with integrated crypto and memory.
OTN, B100G OTN, and FlexO
FPGA-based Virtual ASSPs for OTN, Beyond-100G, and FlexO transport up to 800G.
Flex Ethernet (FlexE) and MTN
FPGAs implement FlexE and MTN to turn Ethernet into a flexible multichannel link.
Private Line Emulation (PLE)
FPGAs enable bit-level transparent OTN transport over IP and Ethernet networks.
EPON-GPON / 10G / 25-50G PON
FPGAs implement scalable OLT MAC solutions from GPON to 50G Asymmetric PON.
Common Questions
An FPGA provides configurable hardware processing for gateway network functions and protocol-specific data paths. Ethernet and PCIe hard IP support integration with the surrounding infrastructure, while programmable logic lets the gateway implementation be tailored to evolving traffic rather than fixed to one processing function.
Choose a reconfigurable data path when gateway functions must adapt to changing protocols or traffic patterns. Programmable logic supports implementation changes on suitable hardware, while fixed-function hardware offers less scope to alter its processing. The selected FPGA resources and interfaces still bound the supported gateway design.
Ethernet hard IP supports the network data path, while PCIe provides a connection to host-side infrastructure. Combining these interfaces with programmable processing helps integrate gateway acceleration into an existing system, with the exact protocol rates and configurations selected to match the intended workload. Explore FPGA Ethernet hard IP for gateway connectivity
No. A transceiver channel-rate capability describes an interface building block, not the throughput of the complete gateway. The implemented network functions, Ethernet and PCIe configurations, and selected FPGA resources must fit together, so evaluate the complete processing path for the intended protocol and traffic requirements.
Check the selected transceiver configuration, Ethernet and PCIe interfaces, and the protocol-specific processing implemented in logic. These are the gateway’s documented acceleration building blocks. Assess their combined fit for the target workload rather than using a maximum channel-rate figure as proof of system performance. Explore Agilex 7 FPGA gateway interface capabilities