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Wireline
Private Line Emulation (PLE)
FPGAs enable bit-level transparent OTN transport over IP and Ethernet networks.
Transparent Transport Over IP
Private Line Emulation enables bit-level transparent transport of OTN and other service protocols with IP routers, without dedicated OTN systems and networks, standardized within the IETF as encapsulated VPWS over packet-switched networks.
PLE breaks the client bit-stream into equal-sized packets encapsulated into Ethernet/MPLS packets, and at the far end, the PLE function evens out latency variations and re-establishes the original bit-stream including its inherent clock.
The Challenges, and Why FPGA
The Challenge
Avoiding Dedicated OTN Networks
Operators want OTN transparency without dedicated OTN systems and networks.
Why FPGA
Bit-Level Transparent Transport
PLE transports OTN bit-streams transparently over IP and Ethernet networks.
The Challenge
Latency Variation & Clock Recovery
Packet networks introduce latency variation that must be evened out.
Why FPGA
Clock Re-Establishment
The PLE function evens out latency and re-establishes the original clock.
The Challenge
Evolving IETF Standards
PLE is still being standardized within the IETF and continues to evolve.
Why FPGA
Field-Upgradeable PLE Design
Reprogrammable FPGAs adapt to the evolving PLE standard in the field.
Why Altera
Bit-Level Transparent Transponders
Multi-channel OTU4 PLE transponders map signals for transport over Ethernet.
Field-Upgradeable Virtual ASSPs
Upgrade Virtual ASSP solutions in the field with more features over time.
Combine PLE with OTN & IP/MPLS
Customers combine PLE with OTN, Ethernet, IP/MPLS, and PTP/SyncE.
Ongoing Standard Adaptation
FPGAs allow ongoing adaptation as the PLE standard evolves within the IETF.
Get Started
More Wireline Applications
NFVi
FPGAs bring hardware acceleration to Network Functions Virtualization Infrastructure.
End-to-End Security
Line-rate Crypto including MACsec and IPsec, plus post-quantum support on Agilex® FPGAs, from access to core, with security you can update in the field.
Gateway
FPGAs implement flexible, reconfigurable hardware acceleration for network gateways.
Routing/Switching Overlay
FPGAs power high-speed routing and switching with integrated crypto and memory.
OTN, B100G OTN, and FlexO
FPGA-based Virtual ASSPs for OTN, Beyond-100G, and FlexO transport up to 800G.
Flex Ethernet (FlexE) and MTN
FPGAs implement FlexE and MTN to turn Ethernet into a flexible multichannel link.
EPON-GPON / 10G / 25-50G PON
FPGAs implement scalable OLT MAC solutions from GPON to 50G Asymmetric PON.
Common Questions
Private Line Emulation transports an OTN or other client bitstream transparently over Ethernet or IP/MPLS. It divides the stream into equal-sized packets, then reconstructs the original stream at the destination, allowing packet-network transport without requiring a dedicated OTN network for that service.
Consider PLE when OTN bit-level transparency is needed across existing Ethernet or IP/MPLS infrastructure. Dedicated OTN transport remains a different network architecture; PLE preserves the client stream through encapsulation and reconstruction, with packet-delay variation and timing recovery becoming part of the implementation.
The terminator uses timestamps inserted by the originator together with a common network frequency signal to re-establish the client clock. It also evens out packet latency variations, so timing reconstruction and bitstream recovery must be considered together rather than treating packet delivery alone as transparent transport.
Check the originator timestamps, the common network frequency signal and the terminator’s handling of latency variation. These are the documented elements used to reconstruct the client clock and bitstream. Receiving the encapsulated packets alone does not verify that the timing-recovery path is functioning as intended.
A multi-channel OTU4 PLE transponder provides a starting point for mapping OTN client signals into packets for Ethernet or IP/MPLS transport. The Triple OTU4-PLE resource helps engineers examine that architecture before adapting the interfaces, timing functions and programmable implementation to their network requirements. Explore OTU4 PLE transponder reference design