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Wireline
EPON-GPON / 10G / 25-50G PON
FPGAs implement scalable OLT MAC solutions from GPON to 50G Asymmetric PON.
One Platform, Every PON Generation
FPGA technology allows operators and vendors to differentiate and optimize their investment in PON networks, with programmability making the FPGA a perfect vehicle for optical disaggregation and avoiding component lock-in.
Altera FPGAs implement OLT solutions leveraging burst mode transceivers, DDR5/LPDDR5 memory interfaces, built-in Ethernet MACs, and core logic to build optimized, differentiated, and future-proof PON MAC solutions with ready-made partner IP cores.
The Challenges, and Why FPGA
The Challenge
Avoiding Component Lock-In
Operators want to avoid being locked into specific optical components.
Why FPGA
Optical Disaggregation
FPGA programmability enables optical disaggregation and vendor flexibility.
The Challenge
Multi-Generation PON Support
Networks must support GPON through 50G Asymmetric PON on one platform.
Why FPGA
Multi-Standard PON MAC TC Layer
One platform addresses data rates from GPON to 50G Asymmetric PON.
The Challenge
Advanced OLT Functions
OLTs increasingly need switching, ACL/LPM, DPI, and AI inference.
Why FPGA
Integrated Advanced Functions
Complement PON functions with switch/router, ACL/LPM, DPI, or AI inference.
Why Altera
Burst Mode Transceiver Support
Leverages burst mode capabilities of transceivers for OLT solutions.
DDR5/LPDDR5 Memory Interfaces
High-speed memory interfaces support demanding PON MAC workloads.
Ready-Made PON-MAC IP Cores
Partner PON-MAC IP cores accelerate differentiated OLT development.
Scalable 50G Asymmetric Support
One platform scales from GPON to 50G Asymmetric with AES and FEC.
Get Started
More Wireline Applications
NFVi
FPGAs bring hardware acceleration to Network Functions Virtualization Infrastructure.
End-to-End Security
Line-rate Crypto including MACsec and IPsec, plus post-quantum support on Agilex® FPGAs, from access to core, with security you can update in the field.
Gateway
FPGAs implement flexible, reconfigurable hardware acceleration for network gateways.
Routing/Switching Overlay
FPGAs power high-speed routing and switching with integrated crypto and memory.
OTN, B100G OTN, and FlexO
FPGA-based Virtual ASSPs for OTN, Beyond-100G, and FlexO transport up to 800G.
Flex Ethernet (FlexE) and MTN
FPGAs implement FlexE and MTN to turn Ethernet into a flexible multichannel link.
Private Line Emulation (PLE)
FPGAs enable bit-level transparent OTN transport over IP and Ethernet networks.
Common Questions
FPGAs provide programmable logic and supporting interfaces for implementing OLT MAC functions with suitable partner PON-MAC IP. Burst-mode transceivers, DDR5/LPDDR5 interfaces and Ethernet MACs support the architecture. The selected IP must match the intended EPON or GPON protocol; programmability alone does not establish support for every standard.
FPGA programmability lets equipment designers adapt PON processing to selected optical components, helping reduce component lock-in. Configurable MAC functions and interfaces support vendor flexibility and differentiated access equipment, while the chosen optics, transceivers and protocol IP must work together in the implemented system.
A multi-standard PON MAC transmission convergence layer provides a programmable foundation for different PON generations. Partner IP, transceiver capabilities, memory interfaces and AES/FEC resources must match the target implementation. Scaling across generations requires evaluating these resources together rather than assuming every configuration fits the same device.
Burst-mode transceivers support PON reception, while DDR5/LPDDR5 interfaces provide memory resources for demanding MAC workloads. They operate alongside programmable processing and Ethernet uplinks. Engineers should assess the combined interface and processing requirements when selecting hardware for an EPON, GPON or higher-rate PON design.
An FPGA can complement PON MAC processing with Ethernet switching and routing, access control lists (ACL), longest prefix match (LPM) search and deep packet inspection (DPI). AES and FEC can also be integrated, with the supported combination determined by the selected device, protocol IP and system requirements.