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Wireline
Routing/Switching Overlay
FPGAs power high-speed routing and switching with integrated crypto and memory.
High-Speed Routing, Secured
Altera FPGAs implement routing and switching applications by leveraging hard-IP protocols like Ethernet and PCIe, essential for high-speed data transfer and communication, with integrated hard crypto blocks saving fabric space and power.
Support for advanced memory technologies such as HBM2E, DDR4, DDR5, LPDDR4, and LPDDR5 is critical for handling large data volumes and ensuring fast access times for data buffering or search functions like ACL and LPM.
The Challenges, and Why FPGA
The Challenge
High-Speed Data Transfer
Routing and switching infrastructure needs high-speed data transfer.
Why FPGA
Hard-IP Ethernet & PCIe
Hard-IP protocols deliver high-speed data transfer and communication.
The Challenge
Secure Data Transmission
Routing infrastructure needs secure data transmission without added latency.
Why FPGA
Integrated Hard Crypto Blocks
Hard crypto blocks save fabric space and power for secure transmission.
The Challenge
Large Data Volume Handling
Buffering and search functions need to handle large, fast-growing data volumes.
Why FPGA
Advanced Memory Support
HBM2E, DDR4/5, and LPDDR4/5 support fast buffering and search functions.
Why Altera
Hard Crypto in Select Variants
Integrated hard crypto blocks save fabric space and power in routing designs.
Broad Memory Technology Support
HBM2E, DDR4, DDR5, LPDDR4, and LPDDR5 handle large data volumes.
High-Frequency Fabric
Large fabric supports high-frequency designs for demanding performance.
ACL/LPM Search Functions
Altera-provided IP supports ACL and LPM search functions in hardware.
Get Started
More Wireline Applications
NFVi
FPGAs bring hardware acceleration to Network Functions Virtualization Infrastructure.
End-to-End Security
Line-rate Crypto including MACsec and IPsec, plus post-quantum support on Agilex® FPGAs, from access to core, with security you can update in the field.
Gateway
FPGAs implement flexible, reconfigurable hardware acceleration for network gateways.
OTN, B100G OTN, and FlexO
FPGA-based Virtual ASSPs for OTN, Beyond-100G, and FlexO transport up to 800G.
Flex Ethernet (FlexE) and MTN
FPGAs implement FlexE and MTN to turn Ethernet into a flexible multichannel link.
Private Line Emulation (PLE)
FPGAs enable bit-level transparent OTN transport over IP and Ethernet networks.
EPON-GPON / 10G / 25-50G PON
FPGAs implement scalable OLT MAC solutions from GPON to 50G Asymmetric PON.
Common Questions
FPGAs combine high-speed interfaces, programmable processing, and memory connectivity to implement routing and switching data paths. Ethernet and PCIe hard IP support data transfer, while fabric resources implement application-specific functions. The reference architecture uses Agilex 7 to combine these capabilities with crypto and memory support.
Ethernet and PCIe hard IP provide dedicated hardware interfaces for high-speed data transfer and communication. In an FPGA routing architecture, these interfaces work alongside programmable logic, memory, and search functions to build the data path. Designers should select a device variant with the interfaces required by their system.
Integrated hard crypto blocks help save FPGA fabric resources and power when implementing secure data transmission. Available in select variants, these dedicated blocks complement routing and switching logic. Device selection should account for the required crypto capabilities, rather than assuming every FPGA includes the same hard crypto resources.
HBM2E and DDR memory support the storage and fast access needed for large-volume buffering and search workloads. The listed technologies include HBM2E, DDR4, DDR5, LPDDR4, and LPDDR5. Engineers should match the selected device’s memory support to the capacity and access requirements of their routing or switching architecture.
ACL searches identify rules for handling network traffic, while LPM searches find the most specific matching address prefix for routing. Altera-provided IP supports these functions in FPGA hardware. Combined with memory resources and high-speed interfaces, they support traffic classification and forwarding decisions within the routing data path.