External Memory Interfaces IP Support Center

The External Memory Interface (EMIF) support page provides design process from start to finish for FPGAs

Introduction 1. Device Selection 2. User Guides and Documentation 3. EMIF IP Generation 4. Board Design and Simulation 5. Debug 6. Training Courses

Introduction

The External Memory Interface (EMIF) support center provides resources for Agilex® 7, Agilex® 5, Agilex® 3, Stratix® 10, Arria® 10, and Cyclone® 10 devices.

You will find information on how to plan, design, implement, and verify your external memory interfaces. You will also find debug, training, and other resource materials on this page.

Get additional support for Agilex® 7 FPGA Interface Protocol Design, Agilex® 5 FPGA Interface Protocol Design, and Agilex® 3 FPGA Interface Protocol Design. These step-by-step guided journeys for standard development flows surface the key critical resources and documentation.

For other devices, search the Device and Product Support Collections.

1. Device Selection

How to Select a Device

Two tools are available to help you select an FPGA based on your memory requirements:

	EMIF Device Selector	EMIF Spec Estimator
Features	Determines memory interfaces needed to achieve a desired bandwidth Calculates bandwidth based on selected memory configurations Displays all Agilex® 7, Stratix® 10, and Arria® 10 FPGAs supporting selected memory interfaces	Determines performance achievable for specific configuration of the selected FPGA device family Displays maximum frequency for each FPGA family, speed grade and EMIF configuration based on filter selections Find and compare performance of each supported external memory interfaces and configurations for our FPGAs
Device Support	Agilex® 7 FPGAs Stratix® 10 FPGAs Arria® 10 FPGAs	All FPGAs
Resources	EMIF Device Selector Tool User Guide	EMIF Spec Estimator Video Tutorial
EMIF Tools	Download EMIF Device Selector for Agilex® 7, Stratix® 10, or Arria® 10 Devices	Open EMIF Spec Estimator Page

How to select an External Memory Intellectual Property (IP)

To learn about the various memory intellectual property (IP) available, refer to the following online training curriculum:

Training Course	Supported Devices	Description
Introduction to Memory Interfaces	Agilex® 7 F-Series and I-Series	This training is part 1 of 4. This first part of the training introduces the memory options available and describes how the architecture of these devices makes such performance possible. Additional training in the series are Integration of Memory Interfaces (part 2), and Verifying Memory Interfaces (part 3), and On-Chip Debugging (part 4)
Introduction to Memory Interfaces IP in FPGA Devices	Agilex® 5	This course covers the different external memory interface options available, as well as the architectural and hard memory controller features for Stratix® 10 and Arria® 10 FPGAs.
DDR5 Memory and the Memory Interface IP	Agilex® 5	This training includes a recording of the "DDR5 Memory and the Memory Interface IP Ask an Expert". In this session, FPGA Apps engineers discuss DDR5 memory technology and answer questions about DDR5 and the memory interface IP.
High Bandwidth Memory (HBM2) Interfaces: Introduction, Architecture	Stratix® 10 MX	This course covers the benefits of integrating High Bandwidth Memory into the Stratix® 10 MX FPGA devices, features and options for the hardened HBM controller, and how to generate the HBM2 IP.
High Bandwidth Memory (HBM2) Interfaces in: HBMC features	Stratix® 10 MX	This course covers the features and options for the hardened HBM controller, and the Arm* AMBA 4 AXI interface between the controller and user logic.

2. User Guides and Documentation

How to find Information on the EMIF IP

For information regarding the External Memory Interface (EMIF) Intellectual Property (IP), refer to the following External Memory Interfaces IP User Guides:

Please refer to 'User Guides' Section

Content Type	Agilex® 7 Device F-Series and I-Series	Agilex® 7 Device M-Series	Agilex® 5 Device	Agilex® 3 Device	Stratix® 10 Device	Arria® 10 Device	Cyclone® 10 Device
IP User Guide	External Memory Interfaces User Guide	External Memory Interfaces User Guide	External Memory Interfaces (EMIF) IP User Guide	External Memory Interfaces (EMIF) IP User Guide	External Memory Interfaces User Guide	External Memory Interfaces User Guide	External Memory Interfaces User Guide
Design Example User Guide	External Memory Interfaces Design Example User Guide	External Memory Interfaces Design Example User Guide	External Memory Interfaces (EMIF) IP Design Example User Guide Device Design Guidelines	Device Design Guidelines	External Memory Interfaces Design Example User Guide	External Memory Interfaces Design Example User Guide	External Memory Interfaces Design Example User Guide
FPGA PHY Lite User Guide	PHY Lite for Parallel Interfaces IP Core User Guide	PHY Lite for Parallel Interfaces IP Core User Guide	PHY Lite for Parallel Interfaces IP Core User Guide	PHY Lite for Parallel Interfaces IP Core User Guide	PHY Lite for Parallel Interfaces IP Core User Guide	PHY Lite for Parallel Interfaces IP Core User Guide	PHY Lite for Parallel Interfaces IP Core User Guide
FPGA HBM2 User Guide	-	-	-	-	High Bandwidth Memory (HBM2) Interface FPGA IP User Guide	-	-
Release Notes	External Memory Interfaces Release Notes	External Memory Interfaces (EMIF) IP Release Notes	External Memory Interfaces (EMIF) IP Release Notes	External Memory Interfaces (EMIF) IP Release Notes	External Memory Interfaces Release Notes	FPGA IP Core Release Notes	External Memory Interfaces Release Notes
Pin-Out Files	Device pin-out and EMIF address/command pin out	Device pin-out and EMIF address/command pin out	Device pin-out and EMIF address/command pin out	Device pin-out and EMIF address/command pin out	Device pin-out and EMIF address/command pin-out	Device pin-out and EMIF address/command pin-out	Device pin-out and EMIF address/command pin-out

3. EMIF IP Generation

How to generate the EMIF IP

For detailed information regarding External Memory Interface (EMIF) Intellectual Property (IP) parameters, refer to the following protocol-specific sections within the following EMIF IP User Guides:

Topic	Agilex® 7 Device F-Series and I-Series	Agilex® 7 Device M-Series	Agilex® 5 Device	Agilex® 3 Device	Stratix® 10 Device	Arria® 10 Device	Cyclone® 10 Device
EMIF IP Parameter Descriptions	DDR4 QDR-IV	DDR4 DDR5 LPDDR5	DDR4 DDR5 LPDDR4 LPDDR5	LPDDR4	DDR3 DDR4 QDR II/II /II Xtreme QDR-IV RLDRAM3 HBM2	DDR3 DDR4 QDR II/II /II Xtreme QDR-IV RLDRAM3 LPDDR3	DDR3 LPDDR3
Note: For more information on How to Generate the EMIF IP, refer to the below User Guides and Training Courses and Videos sections.

Topic

Agilex® 7 Device

F-Series and I-Series

Agilex® 7 Device

M-Series

Agilex® 5 Device

Agilex® 3 Device

Stratix® 10 Device

Arria® 10 Device

Cyclone® 10 Device

EMIF IP Parameter Descriptions

DDR4
QDR-IV

LPDDR4

DDR3
LPDDR3

Note: For more information on How to Generate the EMIF IP, refer to the below User Guides and Training Courses and Videos sections.

How to Perform Functional Simulation

Topic	Agilex® 7 Device F-Series and I-Series	Agilex® 7 Device M-Series	Agilex® 5 Device	Agilex® 3 Device	Stratix® 10 Device	Stratix® 10 MX Device	Arria® 10 Device	Cyclone® 10 Device
Simulating the External Memory Interface	Simulating Memory IP	Simulating Memory IP	Simulating Memory IP	Simulating Memory IP	Simulating Memory IP	Simulating HBM2 IP	Simulating Memory IP	Simulating Memory IP
Generating a EMIF Design Example for Simulation	Design Example for Simulation	Design Example for Simulation	Design Example for Simulation	Design Example for Simulation	Design Example for Simulation	Design Example for Simulation	Design Example for Simulation	Design Example for Simulation
Note: For information on how to verify an EMIF design, refer to the 'Training Courses and Video' section for the 'Verifying Memory Interfaces IP' course.

Topic

Agilex® 7 Device

F-Series and I-Series

Agilex® 7 Device

M-Series

Agilex® 5 Device

Agilex® 3 Device

Stratix® 10 Device

Stratix® 10 MX Device

Arria® 10 Device

Cyclone® 10 Device

Simulating the External Memory Interface

Simulating Memory IP

Simulating HBM2 IP

Simulating Memory IP

Generating a EMIF Design Example for Simulation

Design Example for Simulation

Note: For information on how to verify an EMIF design, refer to the 'Training Courses and Video' section for the 'Verifying Memory Interfaces IP' course.

Where to find Information on FPGA Resource and Pin Placement

For detailed External Memory Interface (EMIF) pin information, refer to the following protocol-specific sections within the following EMIF Intellectual Property (IP) User Guides:

Topic	Agilex® 7 Device F-Series and I-Series	Agilex® 7 Device M-Series	Agilex® 5 Device	Agilex® 3 Device	Stratix® 10 Device	Arria® 10 Device	Cyclone® 10 Device
EMIF Pin and Resource Planning	DDR4 QDR-IV	DDR4 DDR5 LPDDR5	DDR4 DDR5 LPDDR4 LPDDR5	LPDDR4	DDR3 DDR4 QDR II/II /II Xtreme QDR-IV RLDRAM3	DDR3 DDR4 QDR II/II /II Xtreme QDR-IV RLDRAM3 LPDDR3	DDR3 LPDDR3

Topic

Agilex® 7 Device

F-Series and I-Series

Agilex® 7 Device

M-Series

Agilex® 5 Device

Agilex® 3 Device

Stratix® 10 Device

Arria® 10 Device

Cyclone® 10 Device

EMIF Pin and Resource Planning

DDR4
QDR-IV

LPDDR4

DDR3
LPDDR3

Interface Planner

For information on Interface Planner for resource location assignments, refer to the following online training.

Training Course	Description
Fast & Easy I/O System Design with Interface Planner	This course covers how to implement a design resource floorplan using Interface Planner. Learn about Interface Planner, formerly known as BluePrint, an easy-to-use tool in the Quartus® Prime Pro Edition software that uses the power of the Fitter to create a legal floorplan in minutes.

Additional Resources for PHY Lite for Parallel Interfaces

Topic	Supported Device	Description
PHY Lite for Parallel Interfaces FPGA IP User Guide	Agilex® 3 FPGA C-Series Agilex® 5 FPGA D-Series and E-Series Agilex® 7 FPGA F-Series, I-Series, and M-Series Stratix® 10 FPGA Arria® 10 FPGA Cyclone® 10 GX FPGA	The main use of the PHY Lite for Parallel Interfaces IP is for building custom memory interface PHY blocks. It is suitable for simple parallel interfaces. The user guide provides instructions on interfacing with protocols such as DDR2, LPDDR2, LPDDR, TCAM, Flash, ONFI (synchronous mode), and mobile DDR.

Generating Multiple EMIF Designs

Topic	Supported Device	Description
How to run Agilex® Multiple EMIF Designer Tool	Agilex® 7 M-Series Device Agilex® 5 Device Agilex® 3 Device	The Agilex Multiple EMIF Designer Tool streamlines and automates the merging of multiple Agilex FPGA EMIF designs, ensuring seamless integration. For step-by-step instruction on how to use the tool and to download the tool, you can refer to the following knowledge article: Agilex® Multiple EMIF Designer Tool

Topic

Supported Device

Description

How to run Agilex® Multiple EMIF Designer Tool

Agilex® 7 M-Series Device
Agilex® 5 Device
Agilex® 3 Device

The Agilex Multiple EMIF Designer Tool streamlines and automates the merging of multiple Agilex FPGA EMIF designs, ensuring seamless integration.

For step-by-step instruction on how to use the tool and to download the tool, you can refer to the following knowledge article:

Agilex® Multiple EMIF Designer Tool

4. Board Design and Simulation

Where to Find Information on Board Layout and Design

For detailed External Memory Interface (EMIF) board layout and design information, refer to the following protocol-specific sections within the following EMIF Intellectual Property (IP) User Guides:

Topic	Agilex® 7 Device F-Series and I-Series	Agilex® 7 Device M-Series	Agilex® 5 Device	Stratix® 10 Device	Arria® 10 Device	Cyclone® 10 Device
EMIF Board Design Guidelines	DDR4 QDR-IV	DDR4 DDR5 LPDDR5	DDR4 DDR5 LPDDR4 LPDDR5	DDR3 DDR4 QDR II/II /II Xtreme QDR-IV RLDRAM3	DDR3 DDR4 QDR II/II /II Xtreme QDR-IV RLDRAM3 LPDDR3	DDR3 LPDDR3

Topic

Agilex® 7 Device

F-Series and I-Series

Agilex® 7 Device

M-Series

Agilex® 5 Device

Stratix® 10 Device

Arria® 10 Device

Cyclone® 10 Device

EMIF Board Design Guidelines

DDR4
QDR-IV

DDR3
LPDDR3

How to Perform Board/Channel Simulation

For information on measuring write-and-read Intersymbol Interference (ISI) and Crosstalk, arranging Command, Address, Control and Data pins, and I/O bank placement restrictions, refer to the following guidelines:

How to Calculate Board Skew and Channel Loss

Topic	Board Skew Parameter Tool	Channel Loss Calculation Tool
Features	Calculates board skew due to PCB traces and multi-rank designs	Calculates channel loss due to Intersymbol Interference (ISI) and Crosstalk on Command, Address, Control, and Data signals
Support	Arria® 10 and Stratix® 10 FPGAs All memory protocols	Arria® 10 and Stratix® 10 FPGAs DDR memory protocols Compatible with Mentor Graphics HyperLynx Signal Integrity software only
Tools	Download Board Skew Parameter Tool	Download Channel Loss Tool

Where to Find Information on Timing Closure

For information regarding External Memory Interface (EMIF) timing closure, refer to the following section within the EMIF Intellectual Property (IP) User Guides.

Agilex® 7 Device F-Series and I-Series	Agilex® 7 Device M-Series	Agilex® 5 Device	Stratix® 10 Device	Arria® 10 Device	Cyclone® 10 Device
EMIF IP Timing Closure	EMIF IP Timing Closure	EMIF IP Timing Closure	EMIF IP Timing Closure	EMIF IP Timing Closure	EMIF IP Timing Closure

Agilex® 7 Device

F-Series and I-Series

Agilex® 7 Device

M-Series

Agilex® 5 Device

Stratix® 10 Device

Arria® 10 Device

Cyclone® 10 Device

EMIF IP Timing Closure

5. Debug

How to Debug External Memory Interface Designs

For information regarding debugging the external memory interface (EMIF) intellectual property (IP), refer to the following section within the EMIF IP User Guides.

Agilex® 7 Device	Agilex® 5 Device	Agilex® 3 Device	Stratix® 10 Device	Arria® 10 Device	Cyclone® 10 Device
EMIF IP Debugging User Guide Download EMIF Debug HTML Guide	EMIF IP Debugging User Guide	EMIF IP Debugging User Guide	EMIF IP Debugging User Guide Download EMIF IP Debug HTML Guide	EMIF IP Debugging User Guide	EMIF IP Debugging User Guide

How to Use the EMIF Debug Toolkit

Training Course	Description
EMIF Toolkit and On-Chip Debug Toolkit of Memory Interfaces IP in FPGA Devices	This course covers how to perform debug using the EMIF Toolkit or On-Chip Debug Toolkit, how to use Traffic Generator 2.0, and configure multiple memory interface designs for compatibility with these debug tools.

Description of features, support and accessibility of the EMIF Debug Toolkit:
Features	Displays pre and post calibration margins per DQS group and DQ pin Generates read/write eye diagrams per DQ pin (2-D eye diagram) Allows customizable real-time traffic generator for test/debug (Traffic Generator 2.0) Captures read/write margins during user-mode traffic (Driver Margining)
Support	Compatible with EMIF design example projects and custom EMIF designs containing one or more memory interfaces Supports all memory protocols
Accessibility	Accessible through the Quartus Prime software (Tools > System Debugging Tools > External Memory Interface Toolkit)

Mailbox Command Execution Script

Topic	Supported Device	Description
External Memory Interfaces (EMIF) Mailbox Script	Agilex® 7 M-Series Device Agilex® 5 Device Agilex® 3 Device	The Mailbox Access Script available to allow you test the command execution. For step-by-step instruction on how to perform Mailbox access, refer to the following user guide: Agilex® 7 M-Series FPGA (EMIF) IP User Guide: IOSSM Mailbox Access Script Agilex® 5 FPGAs and SoCs (EMIF) IP User Guide: IOSSM Mailbox Access Script Agilex® 3 FPGAs and SoCs (EMIF) IP User Guide: IOSSM Mailbox Access Script

Topic

Supported Device

Description

External Memory Interfaces (EMIF) Mailbox Script

Agilex® 7 M-Series Device

Agilex® 5 Device

Agilex® 3 Device

The Mailbox Access Script available to allow you test the command execution.

For step-by-step instruction on how to perform Mailbox access, refer to the following user guide:

Optimizing Controller Performance

For information regarding controller performance and efficiency, refer to the following section within the External Memory Interfaces (EMIF) Intellectual Property (IP) User Guides.

Agilex® 7 Device F-Series and I-Series	Agilex® 7 Device M-Series	Agilex® 5 Device	Agilex® 3 Device	Stratix® 10 Device	Arria® 10 Device	Cyclone® 10 Device
Controller Optimization	Controller Optimization	Controller Optimization	Controller Optimization	Optimizing Controller Performance High Bandwidth Memory (HBM2) Controller Performance	Optimizing Controller Performance	Optimizing Controller Performance

Agilex® 7 Device

F-Series and I-Series

Agilex® 7 Device

M-Series

Agilex® 5 Device

Agilex® 3 Device

Stratix® 10 Device

Arria® 10 Device

Cyclone® 10 Device

Controller Optimization

Controller Optimization

Controller Optimization

Controller Optimization

Optimizing Controller Performance

Optimizing Controller Performance

Additional EMIF Debugging Resources

Topic	Supported Device	Description
Traffic Generator 2.0 User Guide	Agilex® 7 F-Series and I-Series Devices	The Traffic Generator 2.0 allows you to test and debug your external memory interface through customizable traffic and test patterns. Refer to the following guide and videos for detailed information on how to use the Traffic Generator 2.0 feature.
EMIF Example Traffic Generator Video	Arria® 10 Device	Learn how to implement different test patterns on the Arria 10 traffic generator for external memory interface.

6. Training Courses

Agilex® 7 Device F-Series and I-Series	Stratix® 10 Device	Arria® 10 Device	Cyclone® 10 Device
Introduction to Memory Interfaces Integration of Memory Interfaces Verifying Memory Interfaces On-Chip debugging of Memory Interfaces HLS Data Types Fast and Easy I/O System Design with Interface Planner	Introduction to Memory Interfaces Integrating Memory Interfaces Verifying Memory Interfaces On-Chip Debugging of Memory Interfaces High Bandwidth Memory (HBM2) Interfaces: Introduction, Architecture High Bandwidth Memory (HBM2) Interfaces: HBMC features	Introduction to Memory Interfaces Integrating Memory Interfaces Verifying Memory Interfaces On-Chip Debugging of Memory Interfaces	Introduction to Memory Interfaces Integrating Memory Interfaces Verifying Memory Interfaces On-Chip Debugging of Memory Interfaces

Agilex® 7 Device

F-Series and I-Series

Stratix® 10 Device

Arria® 10 Device

Cyclone® 10 Device

Additional Recommended User Guides

For information regarding the External Memory Interface (EMIF) Intellectual Property (IP), refer to the following EMIF IP User Guides.

Agilex® 7 Device F-Series and I-Series	Agilex® 7 Device M-Series	Agilex® 5 and Agilex® 3 Devices	Stratix® 10 Device	Arria® 10 Device	Cyclone® 10 Device
Performance Monitor User Guide Test Engine User Guide PHY Lite for Parallel Interfaces	PHY Lite for Parallel Interfaces	Performance Monitor User Guide Test Engine User Guide PHY Lite for Parallel Interfaces	External Memory Interfaces High Bandwidth Memory (HBM2) Interface PHY Lite for Parallel Interfaces	External Memory Interfaces PHY Lite for Parallel Interfaces	External Memory Interfaces PHY Lite for Parallel Interfaces

Agilex® 7 Device

F-Series and I-Series

Agilex® 7 Device

M-Series

Agilex® 5 and Agilex® 3 Devices

Stratix® 10 Device

Arria® 10 Device

Cyclone® 10 Device

PHY Lite for Parallel Interfaces

How to Learn About Known Issues Regarding EMIF

For information on current and known issues regarding the EMIF IP, refer to the Knowledge Base:

Additional Documentation

Comprehensive list of FPGA devices and product collections categorized by product lifecycle stages.

FPGA Device and Product Support Collections

Additional Training Courses for External Memory Interfaces

FPGA Technical Training Catalog

For additional information, search the following resources: Documentation, Training Courses, Design Examples, and Knowledge Base.