Modern wireless communication systems often employ sophisticated, non-constant envelope schemes, such as WCDMA and OFDM, to achieve high-spectral efficiency. Due to the inherent nature of these technologies, these signals often have a high peak-to-average ratio (PAR) that places demands on the data converters and adversely impacts the efficiency of power amplifiers (PAs) used in wireless basestations. Reducing the PAR increases PA efficiency, allowing higher average power to be transmitted before saturation occurs.
Crest factor reduction (CFR) is a digital technique used to limit the dynamic range of the signals transmitted in wireless communications and other applications. In a modern transmit chain, CFR is often incorporated with digital predistortion (DPD), which acts to linearize the PA, allowing operation at maximum efficiency with spectral compliance. CFR is helpful to DPD because it reduces the dynamic range of the signal, easing linearization.
A CFR processor in the context of a typical remote radio head (RRH) solution is shown in Figure 1. The CFR is situated after the digital up conversion (DUC) stage and prior to any equalization or DPD forward path filtering. Multiple copies of the CFR (and other RRH modules) can be used to support two or more transmit antennas.
Figure 1: Altera CFR within a Typical Remote Radio Head Solution
The Altera® Crest Factor Reduction reference design is a high-performance, highly parameterizable crest factor reduction processor, designed and delivered using Altera DSP Builder Advanced Blockset tool.
Altera Crest Factor Reduction reference design is based on the peak cancellation algorithm. It employs nonlinear saturation around the peaks to reduce the PAR.
The main principle behind the peak cancellation technique is to iteratively cancel the signal peaks by a set of impulse generating kernels. These kernel impulses are generated in advance according to the characteristics of the input signals and pre-loaded onto the system before the start-up. Therefore multiple air interface standards are enabled using the same system by suitably changing the filters used to generate the pulse.
Figure 2 shows the basic structure of a single iteration of the CFR processor. Input waveform “x” is fed to the peak detection unit which calculates where x exceeds a predetermined peak magnitude threshold (see peak threshold subplot). The output from peak detection is used to generate kernel impulses aligned to signal peaks. Kernel generation happens in hardware by reading from one of a number of pulse memories. One suitable choice for a kernel is the sinc pulse. Multiple kernels can generated at once by having greater than one pulse memory. Each kernel function is aligned (scaled and rotated) to the center sample of the input waveform x. Overlapping kernel functions are summed to create a cancellation waveform. The sum cancellation waveform is subtracted from a delayed version of the original input x to produce the PAR reduced output waveform.
Figure 2: Algorithm Summary Showing Basic Structure of CFR Processor for Single Iteration