Crest Factor Reduction
Modulated Waveform Characteristics in 3G Systems
The composite downlink signal transmitted by basestations in 3G code-division multiple access (CDMA)-based systems is formed by summing up different physical channels, as shown in Figure 1. The different physical channels include dedicated data and control channels for different users apart from common control channels that are always required.
Figure 1. Downlink WCDMA Model for a Single Carrier
As the number of users in the system increases, the time-varying envelope of the composite signal exhibits a high peak-to-average ratio (PAR) or crest factor. The crest factors of the downlink signals are as high as 15 dB for single carrier systems and 20 dB for basestations with multiple carriers.
Impact on Power Amplifier Efficiency
Signals with high crest factors degrade the efficiency of the power amplifiers that amplify the downlink signals in basestation transmitters. The operating point of the power amplifier (PA) is typically reduced, or backed off, to accommodate the peaks of the input signal. This is done to maintain linearity at the PA output and prevent out-of-band radiation. Input signals with a high crest factor will need large back-off and will lower the efficiency of the PA. It is therefore important to reduce the crest factor of the input signal and prevent the efficiency of the PA from falling to unacceptable levels.
Crest Factor Reduction Techniques
Clipping the peaks of the signal is the simplest way of reducing the crest factor. However, hard clipping causes sharp corners in the clipped signal, degrading signal quality and increasing the out-of-band radiation. (1)
Peak windowing, shown in Figure 2, is a technique that smoothes the sharp corners by multiplying the signal to be clipped with a windowing function.
Figure 2. Peak Windowing to Reduce Crest Factor
The magnitude of the original signal x(n) is compared with a threshold value A to yield an intermediate scaling factor c(n). This is then convolved with the window coefficients w(n) to generate the final windowed scaling factor b(n), as shown below:
A windowing finite impulse response (FIR) filter with a feedback structure, as shown in Figure 3, can be used to calculate the clipping function b(n). The feedback structure is used to calculate a correction term using the previous input values to prevent overclipping of consecutive samples. The choice of the length of the window L involves a trade-off between the signal quality and the out-of-band radiation and has to be chosen appropriately to satisfy the basestation radio transmission requirements. You can find more information on the algorithm in the document listed in the note below.
Note:
- "Effect of Clipping in Wideband CDMA System and Simple Algorithm for Peak Windowing,” Olli Vaananen, Jouko Vankka, and Kari Halonen— Helsinki University of Technology, Finland.
Figure 3. FIR Filter Structure with Feedback
Altera Crest Factor Reduction Implementation
Altera’s Stratix® series FPGAs with embedded digital signal processing (DSP) blocks and Nios® II soft processors offer an ideal platform to implement crest factor reduction solutions. This section describes the proposed implementation of the peak windowing algorithm using Stratix series FPGAs.
You can implement the windowing algorithm prior to the pulse shaping operation at baseband, or at intermediate frequency (IF) after pulse shaping and upconversion to the first IF stage. When implemented in baseband, an adaptive version of the algorithm has to be implemented to account for the regrowth in the crest factor of the signal due to the pulse shaping operation that follows. This is not required when implemented at IF. Moreover, in multicarrier (MC) basestations that employ a single MC-PA, the different carriers are summed up in IF prior to combined amplification. The combined signal can exhibit a regrowth in the crest factor even if baseband clipping was employed individually for each carrier.
Altera’s crest factor reduction implementation at digital IF for a multicarrier basestation transmitter is shown in Figure 4.
Figure 4. Crest Factor Reduction Implementation with Altera’s Stratix Series FPGAs
Notes:
- Point S in Figure 1
- DPD = digital predistortion
Amplitude Calculations with CORDIC
The instantaneous amplitude of the complex symbols can be efficiently calculated with Altera’s coordinate rotation digital computer (CORDIC) solution. CORDIC is an iterative algorithm that performs various trigonometric functions by using only additions, subtractions, and shift operations. The Altera® CORDIC uses logic elements (LEs) operating in “arithmetic mode,” where each LE is configured to contain a full adder/subtractor cell plus an associated register. The deeply pipelined, parallel architecture enables operation speeds over 300 MHz.
DSP Blocks for Windowing Filter Implementation
The FIR filter required to implement the peak windowing algorithm can be efficiently implemented using the embedded DSP blocks available in Stratix series FPGAs. Each DSP block has a number of multipliers, followed by adder/subtractor/accumulators, in addition to registers for pipelining. You can use the FIR compiler MegaCore® function to calculate the window filter coefficients and automatically generate the code required for the Quartus® II software to synthesize high-speed, area-efficient FIR filters of various architectures.
Control Logic on the Nios II Embedded Processor
You can implement the control logic required for time sharing the resources of the DSP blocks between the forward and feedback paths of the windowing filter on flexible embedded Nios II processors. In addition, the operations involved in determining the necessity of clipping and calculating the input parameter c(n) for the windowing filter can also be done on Nios II processors. Nios II processors are soft core and can use custom instructions for hardware acceleration of program code. The flexibility of Nios II processors enables you to implement custom adaptive baseband solutions without getting too involved with scheduling complex datapaths.
Altera Advantages for Crest Factor Reduction
Flexibility
Systems that implement crest factor reduction must be flexible enough to adapt to the future improvements in data converter and power transistor technologies. They should also be able to support different configurations (single carrier vs. multicarrier) and multiple standards (wideband code-division multiple access (WCDMA), CDMA2000, enhanced data for GSM evolution (EDGE) etc). Altera devices provide this flexibility.
Integrated Solution
The advanced architectural features of Stratix series FPGAs combined with the enhanced Nios II embedded processors enable a highly integrated solution, which can include a digital upconverter, crest factor reducer, digital predistorter, digital downconverter, resampler, data reformatter, and LVDS I/O transceivers in a single chip.
NRE Cost
Because the demand for third-generation systems cannot be accurately predicted, it is difficult to justify the high non-recurring engineering (NRE) costs associated with ASICs when developing a system. Altera HardCopy® ASICs are low-cost, time-saving alternatives to standard ASICs for high-volume production.
Time-to-Market
Altera offers significant time-to-market advantages for FPGA, CPLD, and HardCopy designs with the Quartus II design software and its SOPC Builder system-generation tool that make integrating intellectual property (IP) cores at the system level easier than ever before.
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