Literature: Stratix III Devices
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- Chapter 1. Stratix III Device Family Overview (ver 1.3, Nov 2007, 239 KB)
- Chapter 2. Logic Array Blocks & Adaptive Logic Modules in Stratix III Devices (ver 1.2, Oct 2007, 219 KB)
- Chapter 3. MultiTrack Interconnect in Stratix III Devices (ver 1.1, Oct 2007, 151 KB)
- Chapter 4. TriMatrix Embedded Memory Blocks in Stratix III Devices (ver 1.3, Nov 2007, 306 KB)
- Chapter 5. DSP Blocks in Stratix III Devices (ver 1.2, Oct 2007, 339 KB)
- Chapter 6. Clock Networks & PLLs in Stratix III Devices (ver 1.3, Nov 2007, 757 KB)
Related Documentation
- AN 435: Design Guidelines for Implementing DDR and DDR2 SDRAM Interfaces in Stratix III Devices (ver 1.0, Feb 2007, 1,465 KB)
- AN 436: Design Guidelines for Implementing DDR3 SDRAM Interfaces in Stratix III Devices (ver 2.0, Dec 2007, 1,139 KB)
- AN 438: Constraining and Analyzing Timing for External Memory Interfaces in Stratix III and Cyclone III Devices (ver 3.0, Oct 2007, 306 KB)
- AN 461: Design Guidelines for Implementing QDRII+ and QDRII SRAM Interfaces in Stratix III Devices (ver 1.0, Jun 2007, 834 KB)
- AN 462: Implementing Multiple Memory Interfaces Using the ALTMEMPHY Megafunction (ver 1.1, Oct 2007, 1,377 KB)
Example Design for AN 462: top.qar (2,313 KB)
- External DDR Memory PHY Interface Megafunction User Guide (ALTMEMPHY) (ver 4.1, Dec 2007, 1,787 KB)
- Utilizing Leveling Techniques in DDR3 SDRAM Memory Interfaces (ver 1.0, Nov 2007, 811 KB)
- Stratix_III_Advertorial (ver 1.0, Aug 2007, 97 KB)
- Accelerating High-Performance Computing With FPGAs (ver 1.1, Oct 2007, 955 KB)
- AN 437: Power Optimization in Stratix III FPGAs (ver 2.0, Aug 2007, 219 KB)
- AN 448: Stratix III Power Management Design Guide (ver 1.3, May 2007, 200 KB)
- Stratix III PowerPlay Early Power Estimator (ver 7.2 SP1, Oct 2007, 18 KB)
PowerPlay Early Power Estimator User Guide For Stratix III FPGAs (2,561 KB)
- Stratix III Programmable Power (ver 1.1, May 2007, 631 KB)
- AN 454: Implementing PLL Reconfiguration in Stratix III Devices (ver 1.1, Oct 2007, 543 KB)
Design Example 1 (363 KB)
Design Example 2 (210 KB)
- AN 465: Implementing OCT Calibration in Stratix III Devices (ver 1.0, Nov 2007, 623 KB)
Design Example 1 (200 KB)
Design Example 2 (74 KB)
Design Example 3 (211 KB)
Stratix III OCT Power Up Example (46 KB)
- AN 476: Impact of I/O Settings on Signal Integrity in Stratix III Devices (ver 1.0, Oct 2007, 391 KB)
- AN 518: SGMII Interface Implementation Using Soft-CDR Mode of Stratix III Devices (ver 1.0, May 2008, 1,070 KB)
- Stratix III FPGA Signal Integrity (ver 1.0, Nov 2006, 797 KB)
- Altera Addresses the SWaP Challenges (ver 1.0, Sep 2007, 148 KB)
- Altera Enhanced COTS PLD Initiative (ver 1.0, Sep 2007, 138 KB)
- Stratix_III_Advertorial (ver 1.0, Aug 2007, 97 KB)
- 1080p video framework from Altera (ver 1.0, Apr 2008, 229 KB)
- Accelerating applications on coprocessing platforms (ver 1.0, Jul 2007, 103 KB)
- Altera FPGAs for radar and advanced sensors (ver 1.0, Oct 2008, 219 KB)
- Altera wireless solutions - 3GPP Long-Term Evolution (ver 1.0, Jan 2008, 68 KB)
- Broadcast Solutions Supporting Altera's HD Quality Initiative (HDQI) (ver 2.0, Apr 2008, 1,703 KB)
- Development boards for broadcast applications (ver 2.0, Apr 2008, 122 KB)
- Altera Product Catalog 2007 (ver 4.1, Sep 2007, 2,597 KB)
- Altera's Strategy for Delivering the Benefits of the 65-nm Semiconductor Process (ver 1.1, Sep 2006, 344 KB)
- Design Security in Stratix III Devices (ver 1.4, Nov 2006, 287 KB)
- Designing and Using FPGAs for Double-Precision Floating-Point Math (ver 1.1, Aug 2007, 683 KB)
- First-In-First-Out Megafunction User Guide (FIFO) (ver 4.0, May 2007, 959 KB)
dcfifo_in_legacy_mode.qar (Example 3) (268 KB)
dcfifo_in_show_ahead_mode.qar (Example 4) (223 KB)
dcfifo_narrow_write_wide_read.qar (Example 6) (227 KB)
dcfifo_wide_write_narrow_read.qar (Example 5) (231 KB)
scfifo_in_legacy_mode.qar (Example 1) (36 KB)
scfifo_in_show_ahead_mode.qar (Example 2) (37 KB)
- Guidance for Accurately Benchmarking FPGAs (ver 1.2, Dec 2007, 847 KB)
- Performing Equivalent Timing Analysis Between Altera Classic Timing Analyzer and Xilinx Trace (ver 3.0, Oct 2007, 1,336 KB)
- Performing Equivalent Timing Analysis Between Altera TimeQuest and Xilinx Trace (ver 1.0, Nov 2007, 1,276 KB)
- Robust SEU Mitigation With Stratix III FPGAs (ver 1.0, Feb 2007, 800 KB)
- SEmulation: Turbocharging the FPGA Development Process (ver 1.0, Mar 2007, 1,240 KB)
- Stratix III FPGAs (ver 1.2, Aug 2007, 1,768 KB)
- Stratix III FPGAs vs. Xilinx Virtex-5 Devices: Architecture and Performance Comparison (ver 2.1, Oct 2007, 949 KB)
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