New Additions and Enhancements
The v14.0 release of Altera® intellectual property (IP) features new additions and feature enhancements to the MegaCore® function portfolio.
Digital Signal Processing (DSP):
- Nios II Gen2 Processor (see What's New in Embedded)
External Memory Protocols:
- Support for:
- DDR3/4 ECC mode
- DDR3/4 hard PHY-only mode
- QDR II+Xtreme
- QDR II+
- QDR II
- RLDRAM 3 hard PHY
- New Low Latency 40G Ethernet and 100G Ethermet MegCores for Stratix® V FPGAs for greater than 50% size reduction and 70% lower latency.
- Best-in-class PCI Express® intellectual property solution delivers FPA industry's highest performance. This advanced solution boosts application performance by delivering up to 6.7 GB/s throughput and greater than 400K input/output operations per second (IOPS). New single root I/O virtualization (SR-IOV) with support up to 2 physical functions (PF) and 128 virtual functions (VF).
- 50G Interlaken IP enhanced with latency and resource utilization reductions of 55% and 20%, respectively.
- New JESD204B IP available including transport layer support for Stratix V and Arria® V FPGAs
Video and Image Processing:
- Added basic 4K support to the following Video & Image Processing Suite cores:
- Clocked Video Input
- Clocked Video Output
- Frame Buffer
- Test Pattern Generator
- Color Space Converter
The product page for each Altera IP core details its features and benefits including release-specific enhancements.
IP support for all device families, including the new Generation10 families (Arria 10 and MAX 10 device families), can be found on the All Intellectual Property page. This page provides device support information for Altera IP and Altera partner IP.
Device Support Levels
IP core device support levels are generally the same as the level of device support provided by Quartus II software. Table 1 below defines the support levels and Table 2 indicates the current status. Note that only those devices that did not have final device support in the previous software v13.1 release are listed in the table below. Any exceptions for the software v14.0 release where the IP core device support does not match the Quartus II software device support will be added to this page on or before the end of August 2014.
Table 1. Altera IP Core Device Support Levels
|FPGA Device Families|
The IP core is verified with preliminary timing models for this device family. The IP core meets all functional requirements, but might still be undergoing timing analysis for the device family. It can be used in production designs with caution.
The IP core is verified with final timing models for this device family. The IP core meets all functional and timing requirements for the device family and can be used in production designs.
Table 2. IP Core Device Support Levels
|Device Family||IP Support|
|Arria V SX||Final|
|Cyclone V SX||Final|