New Additions and Enhancements
The Quartus® II software v13.1 release of Altera® intellectual property (IP) features many new additions to the MegaCore® function portfolio.
External Memory Protocols:
- New JESD204B IP available including transport layer support for Stratix® V Arria® V FPGAs
- New DisplayPort MegaCore functions v1.1a and 1.2 for Stratix V devices.
- New 10/100M/1G/10G Ethernet (10M - 10GbE) option to the 10 Gbps Ethernet MAC MegaCore function for Stratix V and Arria V GZ FPGAs.
- New 10/100M/1G/10G Ethernet PHY option of 10GBASE-KR PHY MegaCore function including Synchronous Ethernet (Sync-E) for Stratix V and Arria V GZ FPGAs.
- IEEE 1588 v2 time synchronization option added to the Triple-Speed Ethernet MAC and PHY, 10 Gbps Ethernet MAC, and 10GBASE-R PHY MegaCore functions including the new 10/100M/1G/10G Ethernet (10M-10GbE) MAC and 10/100M/1G/10G Ethernet PHY options.
- RapidIO® MegaCore function now support Gen1 x2 up to 5 Gbps per lane.
Video and Image Processing:
The product page for each Altera IP core details its features and benefits including release-specific enhancements.
IP support for all device families, including the newer 28 nm FPGA families (Stratix V, Arria V GZ, Arria V, and Cyclone V device families), can be found on the All Intellectual Property page. This page provides device support information for Altera IP and Altera partner IP.
Device Support Levels
IP core device support levels are generally the same as the level of device support provided by Quartus II software. Table 1 below defines the support levels and Table 2 indicates the current status. Note that only those devices that did not have final device support in the previous software v13.0 release are listed in the table below. Any exceptions for the software v13.1 release where the IP core device support does not match the Quartus II software device support will be added to this page on or before the end of January 2014.
Table 1. Altera IP Core Device Support Levels
|FPGA Device Families|
The IP core is verified with preliminary timing models for this device family. The IP core meets all functional requirements, but might still be undergoing timing analysis for the device family. It can be used in production designs with caution.
The IP core is verified with final timing models for this device family. The IP core meets all functional and timing requirements for the device family and can be used in production designs.
Table 2. IP Core Device Support Levels
|Device Family||IP Support|
|Arria V GX / GT||Final|
|Arria V SX||Preliminary|
|Arria V GZ||Final|
|Cyclone V GX / GT||Final|
|Cyclone V SX||Preliminary|