New Additions and Enhancements
The v14.1 release of Altera® intellectual property (IP) features new additions and feature enhancements to the MegaCore® function portfolio.
Digital Signal Processing (DSP):
- Nios® II Gen2 Processor (see What's New in Embedded)
External Memory Interfaces:
- All QDR support for Arria® 10 FPGAs now available to be licensed via the QDR Suite
- DDR3/4 RDIMM and LDRIMM - compilation only
- Includes simulation support for DDR4 RDIMM
- Simulation, compilation, and timing closure for the following protocols:
- DDR3/4 Ping Pong PHY
- QDR IV
- X4 DQ/DQS
- Two DQ/DQS sets per I/O lane
- 3 V I/O bank support for memory interfaces
- Low Latency Ethernet enhanced with the inclusion of the 40GBASE-KR4 support with FEC
- New for Arria 10 FPGAs, PCI Express® single root I/O virtualization (SR-IOV) consisting of two physical functions (PF) and 128 virtual functions (VF)
- New PCI Express multichannel direct memory access (DMA) with up to eight channels and prioritization support
- SerialLite III Streaming IP provides a bandwidth increase of 24% (up to 420 Gbps) for Arria 10 FPGAs.
Video and Image Processing:
- New High-Definition Multimedia Interface (HDMI) 1.4 MegaCore with support for both Arria V and Stratix® FPGAs
- Serial Digital Interface (SDI) II IP enhanced with support for Arria 10 FPGAs
- Significant feature enhancements to DisplayPort 1.2 including MST source/sink, pixel clock recovery, and DisplayID
The product page for each Altera IP core details its features and benefits including release-specific enhancements.
Device Support Levels
IP core device support levels are generally the same as the level of device support provided by Quartus® II software. Table 1 below defines the support levels and Table 2 indicates the current status. Note that only those devices that did not have final device support in the previous software v14.0 release are listed in the table below. Any exceptions for the software v14.1 release where the IP core device support does not match the Quartus II software device support will be added to this page on or before the end of January 2015.
Table 1. Altera IP Core Device Support Levels
|FPGA Device Families|
The IP core is verified with preliminary timing models for this device family. The IP core meets all functional requirements, but might still be undergoing timing analysis for the device family. It can be used in production designs with caution.
The IP core is verified with final timing models for this device family. The IP core meets all functional and timing requirements for the device family and can be used in production designs.
Table 2. IP Core Device Support Levels
|Device Family||IP Support|