New Additions and Enhancements
The Quartus® II software v13.0 release of Altera® intellectual property (IP) features many new additions to the MegaCore® function portfolio.
External Memory Protocols:
- Support for DDR3 LRDIMM on Stratix® V devices, RLDRAM II on Arria® V devices, DDR2 and DDR3 SDRAM on Cyclone® V SoC devices, and DDR3 SDRAM on Arria V SoC devices.
- New DisplayPort MegaCore functions v1.1a and 1.2 for Stratix V devices.
- New 10/100M/1G/10G Ethernet (10M - 10GbE) option to the 10 Gbps Ethernet MAC MegaCore function for Stratix V and Arria V GZ FPGA devices.
- New 10/100M/1G/10G Ethernet PHY option of 10GBASE-KR PHY MegaCore function including Synchronous Ethernet (Sync-E) for Stratix V and Arria V GZ FPGA devices.
- IEEE 1588 v2 time synchronization option added to the Triple-Speed Ethernet MAC and PHY, 10 Gbps Ethernet MAC, and 10GBASE-R PHY MegaCore functions including the new 10/100M/1G/10G Ethernet (10M-10GbE) MAC and 10/100M/1G/10G Ethernet PHY options.
- New 50G Interlaken MegaCore function for 28 nm devices.
- New SerialLite III Streaming MegaCore function.
- Area and fMax optimizations for CPRI MegaCore function.
- Stratix V FPGA Hard IP for PCI Express® now has support for Avalon® Memory-Mapped (Avalon-MM) 256 bit datapath bridge, Avalon-MM 64 bit addressing, and general availability of the Configuration Space Bypass mode.
- RapidIO® MegaCore function now support Gen1 x2 up to 5 Gbps per lane.
Video and Image Processing:
- New Video and Image Processing Suite MegaCore function—Broadcast Interlacer supporting pixel-based cadence detection.
The product page for each Altera IP core details its features and benefits including release-specific enhancements.
IP support for all device families, including the newer 28 nm FPGA families (Stratix V, Arria V GZ, Arria V, and Cyclone V device families), can be found on the All Intellectual Property page. This page provides device support information for Altera IP and Altera partner IP.
Device Support Levels
IP core device support levels are generally the same as the level of device support provided by Quartus II software. Table 1 below defines the support levels and Table 2 indicates the current status. Note that only those devices that did not have final device support in the previous software v12.1 release are listed in the table below. Any exceptions for the software v13.0 release where the IP core device support does not match the Quartus II software device support will be added to this page on or before the end of June 2013.
Table 1. Altera IP Core Device Support Levels
|FPGA Device Families||HardCopy ASIC Device Family|
The IP core is verified with preliminary timing models for this device family. The IP core meets all functional requirements, but might still be undergoing timing analysis for the device family. It can be used in production designs with caution.
The IP core is verified with preliminary timing models for the HardCopy® ASIC companion device. The IP core meets all functional requirements, but might still be undergoing timing analysis for the HardCopy ASIC device family. It can be used in production designs with caution.
The IP core is verified with final timing models for this device family. The IP core meets all functional and timing requirements for the device family and can be used in production designs.
The IP core is verified with final timing models for the HardCopy ASIC device family. The IP core meets all functional and timing requirements for the device family and can be used in production designs.
Table 2. IP Core Device Support Levels
|Device Family||IP Support|
|Arria V GX / GT||Preliminary|
|Arria V GZ||Preliminary|