Table 1 contains digital signal processing (DSP) design examples for use in designs for Altera® devices. To see the design example, choose the corresponding icon in the Design Entry Method column.
| Table 1. DSP Design Examples—Functions and Design Entry Methods | |
| Function | Design Entry Method |
|---|---|
Variable Rate Decimation Filter |
Simulink Model |
| Multichannel Farrow Filter |
Simulink Model |
| Sigma-Delta Converter |
Simulink Model |
| Run-Time Reconfigurable Scaler Design Example |
Verilog HDL |
| Verilog Template of Inferring DSP Block in Stratix® III/Stratix IV FPGAs |
Verilog HDL |
| VHDL Template of Inferring DSP Block in Stratix III/Stratix IV FPGAs |
VHDL |
| Upgrading an AtlanticTM Interface Design to an Avalon® Streaming Interface Design | Verilog HDL |
Achieving Unity Gain in Block Floating Point IFFT+FFT Pair  |
Verilog HDL |
| Coefficient Reload FIR Filter |
Verilog HDL |
| Polyphase Modulation With Aliasing for Digital Up-Conversion | Simulink Model |
| Implementing OFDM Modulation and Demodulation | VHDL |
| Designing Digital Down Conversion Systems Using CIC and FIR Filters | Simulink Model |
| Using CIC Decimation Filter With Multi-Channel Support | Simulink Model |
| CIC Interpolation Filter With Multi-Channel Data Support | Simulink Model |
| Deinterlacer Using Weave Mode | Simulink Model |
| Deinterlacer Using Bob Mode | Simulink Model |
| Gamma Correction | Simulink Model |
| YCbCr to RGB Color Space Conversion | Simulink Model |
| Image Frame Resizing Using Scaler | Simulink Model |
| Salt and Pepper Noise Removal Using 2D Median Filter | Simulink Model |
| Video Picture in Picture (PIP) Mixing Using Alpha Blending Mixer | Simulink Model |
| Chroma Resampler Up-Conversion | Simulink Model |
| 2D Sharpening Finite Impulse Response (FIR) Filter | Simulink Model |
| Viterbi Tail-Biting Double-Pass Decoding (Packet Size = Traceback Length) | Simulink Model |
| Viterbi Tail-Biting Double-Pass Decoding (Packet Size = 2 Traceback Length) | Simulink Model |
| Viterbi Tail-Biting Triple-Pass Decoding (Packet Size = Traceback Length) | Simulink Model |
| Complex Finite Impulse Response (FIR) Filter | Simulink Model |
| Bit-Error Rate (BER) Performance Measurement of Viterbi Decoder | Simulink Model |
| Half-Band Filter Using Distributed Arithmetic | Simulink Model |
| Half-Band Filter Using Distributed Arithmetic and Time Domain Multiplexing (TDM) | Simulink Model |
| Half-Band Filter With Reloadable Coefficients | Simulink Model |
| Half-Band Filter Using DSP Blocks | Simulink Model |
| Fast Fourier Transform With 32K Points Transform Length | Verilog HDL |
| Complex Multiplier With Reloadable Coefficients Using Conventional Representation | Simulink Model |
| Complex Multiplier With Constant Coefficients Using Conventional Representation | Simulink Model |
| Complex Multiplier With Variable Coefficients Using Conventional Representation | Simulink Model |
| Complex Multiplier With Reloadable Coefficients Using Canonical Representation | Simulink Model |
| Complex Multiplier With Constant Coefficients Using Canonical Representation | Simulink Model |
| Complex Multiplier With Variable Coefficients Using Canonical Representation | Simulink Model |
| Viterbi Decoder With Node Synchronization | VHDL |
| Signed Multiplier | VHDL |
| Signed Multiplier With Registered I/O | Verilog HDL |
| Signed Multiply-Accumulator | VHDL |
| Signed Multiply-Adder | Verilog HDL |
| Unsigned Multiplier | Verilog HDL |
| Unsigned Multiplier With Registered I/O | VHDL |
| Unsigned Multiply-Accumulator | Verilog HDL |
| Unsigned Multiply-Adder | VHDL |
| 12 x 9 Firm Multiplier | Verilog HDL |
| 12 x 12 Firm Multiplier | Verilog HDL |
| Fully Variable Coefficient Soft Multiplier | Verilog HDL |
| Hybrid Fixed Coefficient Soft Multiplier | Verilog HDL |
| Hybrid Variable Coefficient Soft Multiplier | Verilog HDL |
| Parallel Fixed Coefficient Soft Multiplier | Verilog HDL |
| Parallel Variable Coefficient Soft Multiplier | Verilog HDL |
| Semi-Parallel Fixed Coefficient Soft Multiplier | Verilog HDL |
| Semi-Parallel Variable Coefficient Soft Multiplier | Verilog HDL |
| Sum of Multiplication Fixed Coefficient Soft Multiplier | Verilog HDL |
| Sum of Multiplication Variable Coefficient Soft Multiplier | Verilog HDL |
| Discrete Cosine Transform (DCT) | |
| Basic FIR Filter | |
| Time-Domain Multiplexed FIR Filter | |
| Polyphase Decimation FIR Filter | Verilog HDL |
| Polyphase Interpolation FIR Filter | Verilog HDL |
| Two-Dimensional FIR Filter | Verilog HDL |
| Basic Infinite Impulse Response (IIR) Filter | Verilog HDL |
| Butterworth IIR Filter | Verilog HDL |
| Magnitude Function | Verilog HDL |
Additional examples are available on the DSP Reference Design page.
Design Examples Disclaimer
These design examples may only be used within Altera devices and remain the property of Altera Corporation. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
