TimeQuest Timing Analyzer Resource Center
The TimeQuest timing analyzer is an ASIC-strength static timing analyzer that supports the industry-standard Synopsys Design Constraints (SDC) format. This page provides links to resources for you to learn more about the TimeQuest analyzer.
For resources on the TimeQuest timing analyzer, see the following:
For a brief overview of the TimeQuest analyzer, refer to the Quartus® II TimeQuest Timing Analyzer: SDC-Based FPGA Timing Analysis product feature page.
To search for known TimeQuest issues and technical support solutions, use Altera’s Knowledge Database. You can also visit the Altera Forum to connect to and discuss technical issues with other Altera users.
For further technical support, use mySupport to create, view, and update service requests.
TimeQuest Analyzer Resources
Table 1 provides links to available documentation on the TimeQuest timing analyzer.
Table 2 provides links to available training and demonstrations on the TimeQuest timing analyzer.
| Table 2. TimeQuest Analyzer Training and Demonstrations |
| Title |
Description |
|
TimeQuest Timing Analyzer (English)
(Online Course)
TimeQuest Timing Analyzer (Chinese)
|
You will use the TimeQuest static timing analyzer tool in the Quartus II software to verify performance of an FPGA or HardCopy® ASIC. You will also create timing constraints (i.e., assignments) using the TimeQuest analyzer. You will use supported SDCs and generate timing reports from the TimeQuest analyzer's user interface and from script files.
This is a 1.5 hour online course.
|
Constraining and Analyzing Timing for Source-Synchronous Circuits with TimeQuest
(Online Course) |
This training shows you how to constrain and analyze source-synchronous interfaces with the TimeQuest timing analyzer in the Quartus II software. You will learn the benefits of source-synchronous interfaces as compared to common clock system interfaces. You will be able to write SDC constraints to constrain single data-rate, source-synchronous inputs and outputs. You will also learn to use the TimeQuest timing analyzer to report and analyze timing for source-synchronous outputs and inputs.
This is a 1 hour online course.
|
Constraining and Analyzing Double Data Rate Source Synchronous Interfaces
(Online Course) |
This training provides an introduction to double data rate interfaces and some of the challenges involved in constraining them. You’ll learn about clock and data constraints for inputs and outputs, including two methods of making the constraints. You’ll learn about timing exceptions for the interfaces. Finally, you’ll learn how to analyze source-synchronous interface timing with the TimeQuest timing analyzer in the Quartus II software version 7.1.
This is a 1 hour online course.
|
The Quartus II Software Design Series: Foundation
(Instructor-Led Course) |
You will learn how to use the Quartus II software to develop an FPGA or CPLD. You will create a new project, enter in new or existing design files, compile to your target FPGA or CPLD, and configure your device using the Quartus II programmer to see the design working in-system. You will also enter basic internal and I/O timing constraints and analyze a design for these timing constraints using the TimeQuest analyzer, the timing analyzer in the Quartus II software.
This is an 8 hour instructor-led course. |
The Quartus II Software Design Series: Timing Analysis
(Instructor-Led Course)
|
You will learn advanced features of the Quartus II software that will enable you to verify your FPGA design. You will learn how to constrain and analyze a design for timing, including understanding FPGA timing parameters, writing SDC files, generating various timing reports in the TimeQuest timing analyzer, and applying this knowledge to an FPGA design. You will also estimate FPGA power consumption using Quartus II software tools and EDA simulation tools.
This is an 8 hour instructor-led course. |
|
Switching to the TimeQuest Timing Analyzer
(Online Course)
|
This training gives you an introduction to switching from the Classic Timing Analyzer in the Quartus II software version 7.2 to the TimeQuest timing analyzer. You will learn about the key differences between the two timing analysis engines. The training covers the recommended process to convert a design to the TimeQuest timing analyzer, including how to review results to ensure the conversion proceeded correctly.
This is a 1 hour online course.
|
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