Altera's complete memory interface design solutions address today's high-speed memory interface challenges. Specifically, Altera provides solutions for the memory controller with our high-performance memory controller II (HPMCII), our universal memory PHY (UNIPHY), and our hardened memory interface controller (HMC which includes the controller, PHY and multiported front end (MPFFE)). These solutions support error correction codes (ECC).
Altera's solutions are provided as either advanced device architectures, customizable MegaCore® functions, Quartus® II design software, reference designs, demonstration boards, and/or simulation models. All of which are accompanied by a rich set of technical documentation.
The Board Skew Parameter Tool (XLS) enables easy and precise board skew parameter calculations while saving crucial design time.
Table 1 lists external memory interfaces supported by Altera FPGAs and HardCopy® ASICs. Get more information using our External Memory Interface Spec Estimator.
| Table 1. External Memory Interface Support | |||||||||
| Device | Memory Type | ||||||||
|---|---|---|---|---|---|---|---|---|---|
| DDR3 SDRAM | DDR2 SDRAM | DDR SDRAM | LPDDR2 | MOBILE DDR | RLDRAMII | RLDRAMIII | QDRII SRAM | QDRII+ SRAM | |
| Stratix V (1) | - | - | - | ||||||
| Stratix IV | - | - | - | ||||||
| Stratix III | - | - | - | ||||||
| Stratix II and Stratix II GX | - | - | - | - | |||||
| Stratix and Stratix GX | - | - | - | - | - | - | |||
| Arria V (1) | - | - | |||||||
| Arria II GZ | - | - | - | - | |||||
| Arria II GX | - | - | - | - | |||||
| Arria GX | - | - | - | - | - | - | - | ||
| Cyclone V (1) | - | - | - | - | - | - | |||
| Cyclone IV | - | - | - | - | - | - | |||
| Cyclone III LS | - | - | - | - | - | - | |||
| Cyclone III | - | - | - | - | - | - | |||
| Cyclone II | - | - | - | - | - | - | |||
| HardCopy IV | - | - | - | ||||||
| HardCopy III | - | - | - | ||||||
| HardCopy II | - | - | - | - | |||||
Notes
Related Links
- View the External Memory Interface Handbook (PDF)
- Download Board Skew Parameter Tool (XLS)
- View the demo video and learn how to interface 1,067 Mbps DDR3 DIMM memory to Stratix® IV FPGAs
- Sign up for instructor-led training on interfacing to external memories with Altera® FPGAs
- Debug GUI Users Guide (PDF)
- Debug GUI (ZIP)

