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TSN-SW: TSN Ethernet Switch

Computer Aided Software Technologies, Inc (dba CAST)

Member

The TSN-SW implements a highly flexible, low-latency, multiport TSN Ethernet switch. It supports the hardware functionality for Ethernet bridging according to the IEEE 802.1Q standard and implements the essential TSN timing synchronization and traffic-shaping protocols (i.e. IEEE 802.1AS-2020, 802.1Qav, 802.1Qbv, and 802.1Qbu, 802.1br). Enhanced reliability features can also be supported, using the optional hardware modules for Frame Replication and Elimination for Reliability (IEEE 802.1CB) and Per-Stream Filtering and Policing (IEEE 802.1Qci). Featuring a configurable number of ports, the Layer-2 switch operates in cut-through mode at wire speed and can provide sub-microsecond port-to-port latency. The core is hence suitable for applications with demanding real-time requirements.

The TSN-SW operates efficiently under different usage scenarios and is highly configurable. Users can configure key factors via the core’s control registers: the mapping of VL...

The TSN-SW implements a highly flexible, low-latency, multiport TSN Ethernet switch. It supports the hardware functionality for Ethernet bridging according to the IEEE 802.1Q standard and implements the essential TSN timing synchronization and traffic-shaping protocols (i.e. IEEE 802.1AS-2020, 802.1Qav, 802.1Qbv, and 802.1Qbu, 802.1br). Enhanced reliability features can also be supported, using the optional hardware modules for Frame Replication and Elimination for Reliability (IEEE 802.1CB) and Per-Stream Filtering and Policing (IEEE 802.1Qci). Featuring a configurable number of ports, the Layer-2 switch operates in cut-through mode at wire speed and can provide sub-microsecond port-to-port latency. The core is hence suitable for applications with demanding real-time requirements.

The TSN-SW operates efficiently under different usage scenarios and is highly configurable. Users can configure key factors via the core’s control registers: the mapping of VLAN priority levels to TSN traffic classes, the traffic scheduling and preemption parameters, the treatment of special frames (i.e. broadcast, unknown, & internal), as well as the VLAN ID and MAC lookup tables used for frame forwarding and filtering. The host system can also switch the mode of operation of each individual port from cut-through to store-and-forward to eliminate the propagation of bad frames at the cost of increased latency. The core otherwise operates autonomously and only requires software assistance at runtime for correct time synchronization; a lightweight ptp/802.1AS software stack comes with the core for that purpose.

The TSN-SW uses standard AMBA® interfaces to ease integration. Its control and status registers are accessible via a 32-bit-wide APB bus, and packet data can be exchanged with the host system via AXI-Streaming interfaces with 32-bit data buses. To further expedite and ease the implementation of customer applications, DMA engines providing access to the stream interfaces via a memory-mapped AXI4 master port, and software stacks supporting higher-layer protocols, such as IEEE 802.1Qcc, IEEE 802.1Qca and SNMP, are optionally available.

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Key Features

  • Low-Latency - sub-microsecond port-to-port latency, cut-through or robust store-and-forward mode selectable per port
  • Configurable number of 3 to 24 full-duplex Ethernet ports plus one internal port
  • 10/100/1000 Mbps
  • Port-based VLAN and 802.1Q Tagged VLAN support
  • Port statistics and port mirroring. Automatic aging table.
  • IEEE 802.1AS-2020
  • Traffic shaping per IEEE 802.1Qav & IEEE 802.1Qbv with eight TSN-Queues
  • Frame preemption per IEEE 802.1Qbu and IEEE 802.3br
  • Frame Replication and Elimination per IEEE 802.1CB and Per Stream Filtering and Policing per IEEE 802.1Qci (optionally imple mented in hardware)
  • Path Control and Reservation per IEEE 802.1Qca, and Enhance ments to Stream Reservation Protocol per EEE 802.1Qcc (op tionally implemented in software)
  • Easy System Integration - AMBA® SoC Interfaces - 32-bit APB for register access, 32-bit AXI4-Stream for packet data. Optional AXI4 DMA engine. Requires minimal host assistance.
  • MII, GMII or RGMII, and MDIO Ethernet PHY interface per port

Offering Brief

Offering Brief

Device Family Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST SoC FPGA, Arria® V SX SoC FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE SoC FPGA, Cyclone® V ST SoC FPGA, Cyclone® V SX SoC FPGA, Agilex® 3 FPGAs and SoC FPGAs C-Series, Agilex® 5 FPGAs and SoC FPGAs D-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs M-Series, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX SoC FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Stratix® 10 AX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA, Stratix® 10 TX FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Demo No
Compliance Yes
Latest Quartus Version Supported 24.3.1
Development Language Encrypted Verilog, Verilog

RTL source code or targeted netlist

Testbenches

Sample Simulation and Synthesis scripts

Comprehensive Documentation

Lightweight PTP stack, easily portable to any other RTOS

Ordering Information

TSN-SW

from Direct

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