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Random Access & Multi User NVMe Gen5 IP core (rmNVMe-IP)

DesignGateway Co., Ltd.

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The rmNVMe-IP (Random Access & Multi User NVMe IP Core) is a fully hardware-based solution designed to deliver low-latency, high-performance NVMe™ SSD access without requiring any CPU intervention. Supporting simultaneous write and read transfer, each with independent access control, this IP core enables true parallelism for workloads that demand random and concurrent data access. It’s an ideal solution for applications like database indexing, high-frequency logging, and AI pre-processing where fast, non-sequential data reads and writes are critical. Optimized for PCIe Gen5 on Altera FPGAs, rmNVMe-IP demonstrates exceptional performance, exceeding 2.5 million IOPS for 4KB random write access. With dedicated queues and data buffers per user, the core ensures consistent throughput and eliminates contention between users. Its efficient architecture simplifies system design while enabling high-throughput, multi-user NVMe access—making it a powerful choice for ...

The rmNVMe-IP (Random Access & Multi User NVMe IP Core) is a fully hardware-based solution designed to deliver low-latency, high-performance NVMe™ SSD access without requiring any CPU intervention. Supporting simultaneous write and read transfer, each with independent access control, this IP core enables true parallelism for workloads that demand random and concurrent data access. It’s an ideal solution for applications like database indexing, high-frequency logging, and AI pre-processing where fast, non-sequential data reads and writes are critical. Optimized for PCIe Gen5 on Altera FPGAs, rmNVMe-IP demonstrates exceptional performance, exceeding 2.5 million IOPS for 4KB random write access. With dedicated queues and data buffers per user, the core ensures consistent throughput and eliminates contention between users. Its efficient architecture simplifies system design while enabling high-throughput, multi-user NVMe access—making it a powerful choice for next-generation real-time data processing systems.

Key Features

  • Fully hardware-based design: No CPU & no external memory required
  • Compatible with PCI Express Gen5 for ultra-high-speed data transfer
  • Supports simultaneous 4KB read & write command queues for multi-user access
  • Configurable 4KB command depth: Up to 256
  • Optimized for high performance with minimal FPGA resource usage
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Offering Brief

Offering Brief

Device Family Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series
Offering Status Production
Integrated Testbench No
Evaluation License No
Design Examples Available Yes
Demo Yes
Compliance No
Hardware Platforms Supported Agilex™ 7 FPGA Starter Kit
Latest Quartus Version Supported 23.1.0
Development Language Encrypted VHDL

Encrypted IP core

Reference Designs Quartus Project

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