SATA HCTL IP (SATA3 Host CPUless IP Core)

Overview Key Features Offering Brief What's Included Ordering Information Documentation & Resources Markets

DesignGateway Co., Ltd.

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CPU-less SATA Host IP core is an all-in-one solution integrating the application, transport, and link layers, enabling direct connection to the PHY layer without CPU or DDR usage. The SATA PHY, implemented in HDL to control the transceiver according to the SATA protocol, acts as the interface between the SATA HCTL IP and the SATA device. This PHY design is included in the reference design provided to IP customers.

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Key Features

Proven Reliability: Our IP Core has been extensively tested and deployed by numerous customers in mission-critical aerospace and aviation projects.
CPUless Design: Eliminates the need for a dedicated processor, reducing complexity, power consumption, and potential failure points.
EMC Friendly: SATA III 6Gbps links offer optimal signal integrity, simplifying circuit board design for electromagnetic compatibility and reducing interference risks.
Compact and Efficient: The small footprint is perfect for the FPGA-based solutions with space and energy-constrained applications.
Scalability: Multiple SATA interface for larger capacity and higher performance is easy to implement with lower FPGA resource usage than other solutions.

Offering Brief

Device Family	Arria® 10 SX SoC FPGA, Arria® 10 GX FPGA, Arria® V ST SoC FPGA, Arria® V GX FPGA, Cyclone® 10 GX FPGA, Cyclone® V SX SoC FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status	Production
Integrated Testbench	No
Evaluation License	No
Design Examples Available	Yes
Demo	Yes
Compliance	No
Latest Quartus Version Supported	23.1.0
Development Language	Encrypted VHDL