SHA 256 IP

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DesignGateway Co., Ltd.

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SHA-256 IP is an optimized and efficient implementation of the SHA-256 algorithm, compliant with the FIPS 180-4 standard. It processes 512-bit data blocks in 65 clock cycles, delivering 7.875 Mbps per MHz—equivalent to 1.575 Gbps at 200 MHz. When combined with Design Gateway's data storage and networking IPs, it enables the development of secure, high-performance, and efficient applications.

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Key Features

Support SHA 256-bit standard function
Support input data length up to 2^61-1 bytes (2^64-8 bits)
Super high throughtput rate at 65 clocks per 64 bytes data (1.015625 cycles/byte).
Hash speed up to 1.575 Gbps @ 200MHz.
Simple user interface signals as same as FIFO interface.

Offering Brief

Device Family	Arria® 10 SX SoC FPGA
Offering Status	Production
Integrated Testbench	No
Evaluation License	No
Design Examples Available	Yes
Demo	Yes
Compliance	No
Hardware Platforms Supported	Arria® 10 SX SoC Development Kit
Latest Quartus Version Supported	23.1.0
Development Language	Encrypted VHDL