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SATA 3.0 Bridge Controller

iWave Global

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The SATA 3.0 Bridge Controller IP Core from iWave enables efficient, high-speed data transfer between custom logic in FPGA and SATA-compliant storage devices such as SSDs and HDDs. Fully compliant with the SATA 3.0 specification, the IP supports Gen3 speeds of up to 6 Gbps and provides seamless integration with user logic through a standard AXI interface.

The controller includes built-in support for SATA link initialization, data frame transmission, command processing, and error detection and correction mechanisms. It is designed to be resource-efficient and highly configurable, making it suitable for a wide variety of applications including storage subsystems, data loggers, video surveillance, and embedded computing platforms.

With the support of detailed documentation, reference designs, and integration guidance, iWave’s SATA 3.0 Bridge Controller helps reduce design complexity and development time. It is ideal for designers seeking to add high-t...

The SATA 3.0 Bridge Controller IP Core from iWave enables efficient, high-speed data transfer between custom logic in FPGA and SATA-compliant storage devices such as SSDs and HDDs. Fully compliant with the SATA 3.0 specification, the IP supports Gen3 speeds of up to 6 Gbps and provides seamless integration with user logic through a standard AXI interface.

The controller includes built-in support for SATA link initialization, data frame transmission, command processing, and error detection and correction mechanisms. It is designed to be resource-efficient and highly configurable, making it suitable for a wide variety of applications including storage subsystems, data loggers, video surveillance, and embedded computing platforms.

With the support of detailed documentation, reference designs, and integration guidance, iWave’s SATA 3.0 Bridge Controller helps reduce design complexity and development time. It is ideal for designers seeking to add high-throughput, reliable storage.

Key Features

  • OOB Control is responsible for controlling OOB Signaling, Speed Negotiation
  • Transceiver PHY performs the following functions: Converts 32-bit parallel data to differential Tx data and received Rx serial data to 32-bit parallel data, Clock recovery from serial data, 8B/10B encoding and decoding, Line-rate change, Out-of-Band (OOB) signal generation and detection, Provide status to link layer
  • Link Layer: Consists of Link layer FSM, CRC generator & Scrambler, Scrambles / De-Scrambles, CRC Calculations, Adds/removes the frame envelope and extracts the useful contents of the FIS and passes on for further processing, Handles flow control and transmission & reception errors
  • Bridge Layer: Bridging b/w SATA Device Link layer & SATA Host Link layer, command extraction logic, FIS Extraction logic, Customizable encryption/decryption logic
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Offering Brief

Offering Brief

Device Family Arria® 10 SX SoC FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA
Offering Status Production
Integrated Testbench No
Evaluation License No
Design Examples Available No
Demo No
Compliance No
Hardware Platforms Supported Arria® 10 SX SoC Development Kit
Latest Quartus Version Supported 24.2.0
Development Language Verilog

IP Core

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