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SATA Host Controller

iWave Global

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The SATA Host Controller IP Core from iWave offers a flexible and high-performance solution for interfacing FPGA-based systems with SATA devices such as SSDs and HDDs. Compliant with the AHCI (Advanced Host Controller Interface) and SATA 3.1 specification, this IP core facilitates seamless integration of storage solutions in applications that require high-speed, reliable data transfer. It supports up to 6 Gbps SATA interfaces and offers native command queuing (NCQ) and hot plug support.

Designed for Altera FPGAs, the core leverages AXI or Avalon interfaces for host-side communication, providing developers with flexibility and easy integration into a wide range of systems. The IP core includes software drivers and APIs that enable developers to interact with SATA devices directly from Linux or Windows operating environments.

This IP is ideal for data logging, high-resolution video capture, industrial storage applications, and embedded systems requir...

The SATA Host Controller IP Core from iWave offers a flexible and high-performance solution for interfacing FPGA-based systems with SATA devices such as SSDs and HDDs. Compliant with the AHCI (Advanced Host Controller Interface) and SATA 3.1 specification, this IP core facilitates seamless integration of storage solutions in applications that require high-speed, reliable data transfer. It supports up to 6 Gbps SATA interfaces and offers native command queuing (NCQ) and hot plug support.

Designed for Altera FPGAs, the core leverages AXI or Avalon interfaces for host-side communication, providing developers with flexibility and easy integration into a wide range of systems. The IP core includes software drivers and APIs that enable developers to interact with SATA devices directly from Linux or Windows operating environments.

This IP is ideal for data logging, high-resolution video capture, industrial storage applications, and embedded systems requiring high throughput and low-latency disk access. iWave also provides reference designs and technical support to help reduce time to market and simplify system-level design.

Key Features

  • Phy layer consists of Transceiver available in the FPGA which convert the parallel data to serial
  • Phy layer supports clock recovery from serial data, 8B/10B encoding and decoding, Byte ordering and word alignment and OOB signaling
  • Link layer supports the frame transmission and reception
  • Link layer supports frame formation by adding the envelope and frame decomposition by removing envelope from received data
  • Link layer supports CRC generation and calculation as well as scrambling and descrambling
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Offering Brief

Offering Brief

Device Family Arria® 10 GX FPGA, Arria® 10 SX SoC FPGA, Stratix® 10 SX SoC FPGA
Offering Status Production
Integrated Testbench No
Evaluation License No
Design Examples Available No
Demo No
Compliance No
Hardware Platforms Supported Arria® 10 SX SoC Development Kit
Latest Quartus Version Supported 24.2.0
Development Language Verilog

IP Core

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