RapidIO to AXI Bridge Controller (Silicon Proven IP for Altera Devices)

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Mobiveil Inc.

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Configurable RapidIO-to-AXI bridge IP that pairs with Mobiveil’s GRIO controller to expose a RapidIO host/device port on one side and AXI3/AXI4 on the system side, featuring multi-channel DMA, message and data-streaming modes, and robust error handling. RAB is a technology-independent, system-validated bridge that supports Serial or Parallel RapidIO, 1×/2×/4× lanes, and 64/128/256-bit internal datapaths with up to 256-byte payloads. It offers AXI PIO (configurable AXI slaves), RapidIO PIO (configurable AXI masters), multi-channel read/write DMA, and Message / Data-streaming / mixed operation. Control is via a PBUS register interface. Reliability features include hardware error recovery, exhaustive error reporting, pass-through for packets up to 288 bytes, and accept-all failover. Delivered with configurable RTL, HDL testbench, protocol checkers, bus watchers, performance monitors, and synthesis/verification guides.

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Key Features

Compliant with RapidlO specification, Revision 4.0
Compliant to AMBA AXI protocol AXl3 / AXl4
Supports 32-bit or 38 -bit or 64 bit AXI addressing
AXI PIO operation with configurable number of AXI Slaves
RPIO operation with configurable number of AXI Masters
Multi-channel Read and Write DMA
Message and Datastream
Works with both serial (1x, 2x, 4x) and parallel interfaces, offering flexible integration options.
Features 64/128/256-bit internal data paths, PBUS configuration interface, and supports up to 256-byte payloads.
Includes Pass-Through for RIO packets up to 288 bytes, Accept-All mode for failover, and bypass support.
Supports PIO, DMA, message, data streaming, or mixed modes, with selectable parallel or serial operation.
Offers hardware error recovery with exhaustive error reporting and handling.

Offering Brief

Device Family	Arria® II GX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST SoC FPGA, Arria® V SX SoC FPGA, Cyclone® IV GX FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V ST SoC FPGA, Cyclone® V SX SoC FPGA, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX SoC FPGA, Cyclone® 10 GX FPGA, Stratix® 10 AX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA, Stratix® 10 TX FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status	Production
Integrated Testbench	Yes
Evaluation License	Yes
Design Examples Available	No
Demo	No
Compliance	No
Latest Quartus Version Supported	24.3.1
Development Language	Encrypted Verilog, Verilog