TSN Network Node (IEEE802.1 Time Sensitive Networking Switched End-Node)

Overview Key Features Offering Brief What's Included Ordering Information Documentation & Resources Markets

NetTimeLogic GmbH

Select

The TSN Network Core (Switched End Node) from NetTimeLogic is a standalone Time-Sensitive Networking (TSN) core according to IEEE 802.1, IEEE 1588, and IEC 62439-3 standards. It supports TSN features like time synchronization, scheduling, priority queues, network redundancy, credit-based shaping, cyclic forwarding, and preemption completely in hardware, which allows running TSN protocols completely independent and standalone from the user application. It can run as a redundant endpoint, bridge between a redundant and a non-redundant network, or daisy chain node.

View Partner Website

Partner Product Page

Contact Now

Contact NetTimeLogic GmbH

LeadSource

ASAP Account ID

Record Type Name

Key Features

Up to 8 different priority queues, with freely definable VLAN priorities
Up to 64 phases per cycle according to priority queues
Cycle time and phase durations freely configurable (max 1 ms, min 15.625 us)
Cut-Through (<2us delay @ 1G) or Store-And-Forward frame forwarding
Frame scheduling according to IEEE 802.1 Qbv, Cyclic forwarding according to IEEE 802.1 Qch, Credit based shaper according to IEEE 802.1 Qav, Frame preemption according to IEEE 802.1 Qbu and IEEE 802.3 br can be enabled for the lowest priority to allow maximum bandwidth usage
Synchronization with sub-microsecond accuracy according to IEEE 1588 Default-, Utility- or Power-Profile or according to IEEE 802.1 AS
Supports the HSR and PRP redundancy protocol according to IEC 62439-3 rev 3 with hardware supervision handling and the Frame Replication & Elimination for Reliability (FRER) according to IEEE 802.1 CB
Can run as Dual Attached Node (DAN) or as Redundancy Box (RedBox) or Daisy Chain Node
Two forwarding ports, one internal/interlink port. Interlink port is optional when AXI stream interfaces are used
Supports up to 8 AXI streaming interfaces, one for each priority/phase
Full line speed
AXI4 Light register set or static configuration

Offering Brief

Device Family	Arria® 10 SX SoC FPGA, Cyclone® III FPGA, Cyclone® IV GX FPGA, Agilex® 5 FPGAs and SoC FPGAs E-Series, MAX® 10 FPGA, Cyclone® V SX SoC FPGA, Arria® V GZ FPGA, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Arria® V SX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 SX SoC FPGA, Agilex® 7 FPGAs and SoC FPGAs M-Series, Cyclone® V GT FPGA, Arria® 10 GT FPGA, Arria® V ST SoC FPGA, Arria® 10 GX FPGA, Stratix® 10 TX FPGA, Cyclone® V SE SoC FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Arria® V GX FPGA, Cyclone® V E FPGA, Agilex® 3 FPGAs and SoC FPGAs C-Series, Cyclone® V GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA, Cyclone® V ST SoC FPGA, Agilex® 5 FPGAs and SoC FPGAs D-Series, Stratix® 10 GX FPGA, Arria® V GT FPGA, Cyclone® 10 LP FPGA, Agilex® 7 FPGAs and SoC FPGAs F-Series, Cyclone® 10 GX FPGA, Cyclone® IV E FPGA, Stratix® 10 AX SoC FPGA
Offering Status	Production
Demo	No
Integrated Testbench	Yes
Evaluation License	Yes
Design Examples Available	Yes
Compliance	No
Intertop	IIC
Latest Quartus Version Supported	25.1.0
OS Support	Not Required
Development Language	VHDL