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SyncE Node (Synchronous Ethernet)

NetTimeLogic GmbH

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NetTimeLogic’s Synchronous Ethernet (SyncE) Node is a full hardware (FPGA) only implementation of an ESMC frame Handler and State selector. The whole ESMC frame sending and receiving & decoding as well as State selection according to the selected option mode are implemented in the core, no CPU is required. This allows running SyncE synchronization completely independent and standalone from the user application.

Key Features

  • Synchronous Ethernet (SyncE) Node
  • Supports ESMC and Enhanced ESMC Message according to ITU-T 8264
  • Automatic selection of State according to SSM codes for SyncE option 1 or 2 networks and QL values as defined in ITU-T G.781
  • Manual State override mode
  • Clock Mux Module
  • PPS Generator Module
  • Tx Clock Generator Module
  • Optional numeric frequency adjustment
  • AXI4Lite register set or static configuration
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Offering Brief

Offering Brief

Device Family Arria® 10 SX SoC FPGA, Cyclone® III FPGA, Cyclone® IV GX FPGA, Agilex® 5 FPGAs and SoC FPGAs E-Series, MAX® 10 FPGA, Cyclone® V SX SoC FPGA, Arria® V GZ FPGA, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Arria® V SX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 SX SoC FPGA, Agilex® 7 FPGAs and SoC FPGAs M-Series, Cyclone® V GT FPGA, Arria® 10 GT FPGA, Arria® V ST SoC FPGA, Arria® 10 GX FPGA, Stratix® 10 TX FPGA, Cyclone® V SE SoC FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Arria® V GX FPGA, Cyclone® V E FPGA, Agilex® 3 FPGAs and SoC FPGAs C-Series, Cyclone® V GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA, Cyclone® V ST SoC FPGA, Agilex® 5 FPGAs and SoC FPGAs D-Series, Stratix® 10 GX FPGA, Arria® V GT FPGA, Cyclone® 10 LP FPGA, Agilex® 7 FPGAs and SoC FPGAs F-Series, Cyclone® 10 GX FPGA, Cyclone® IV E FPGA, Stratix® 10 AX SoC FPGA
Offering Status Production
Demo No
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Compliance No
Latest Quartus Version Supported 25.1.0
OS Support Not required
Development Language VHDL

Source Code

Ordering Information

Documentation & Resources

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