100G TCP/IP Stack for Network Acceleration - MLE FPGA IP Core Design

Overview Key Features Offering Brief What's Included Ordering Information Documentation & Resources Markets

Core Benefits: Accelerate CPUs by offloading TCP/UDP/IP processing into programmable logic (“Offloading”). Increase network throughput and reduce transport latency. Bring full TCP/UDP/IP connectivity to FPGAs even if no CPU is available (“Full Acceleration”). Complete and customizable turn-key solutions and IP cores based on the TCP/UDP/IP stack from the Fraunhofer HHI. All MAC/Ethernet/IPv4/UDP/TCP processing is implemented in HDL code, synthesizable to modern FPGAs and ASIC. User applications can either be implemented in FPGA logic or in software via application-specific interfaces to CPUs.

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Key Features

Highly modular TCP/UDP/IP stack implementation in synthesizable HDL
Full line rate of 70 Gbps or more in FPGA, 100 Gbps or more in ASIC
128-bit wide bi-directional data paths with streaming interfaces
Multiple, parallel TCP engines for scalable processing
Network Interface Card functionality with Bypass (optional)
DPDK Stream interface (optional)
Corundum NIC integration with performance DMA and PCIe (optional)

Offering Brief

Device Family	Agilex® 5 FPGAs and SoC FPGAs D-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs M-Series, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, Cyclone® 10 GX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA
Offering Status	Production
Integrated Testbench	No
Evaluation License	No
Design Examples Available	Yes
Demo	No
Compliance	No
Latest Quartus Version Supported	25.1.1
Development Language	Encrypted Verilog, Encrypted VHDL, Verilog, VHDL