partner-offering-banner.png

Scalable Ultra-High Throughput VESA DSC 1.2b Decoder

Alma Technologies S.A.

Select

The UHT-DSC-D core from Alma Technologies is an advanced decoder, compliant to the VESA Display Stream Compression (DSC) v1.2b standard. It supports decoding of 4:4:4, 4:2:2 and 4:2:0 video streams with 8 to 16 bits per component color depth. The core is scalable and it is available for Altera FPGA and SoC based designs.

The UHT-DSC-D is designed using internal (on-chip) memory blocks only, with simple and fully controllable streaming input and output interfaces. It is a complete and autonomous decoder, not needing any host system CPU or GPU support for its operation. Being carefully designed and rigorously verified, the UHT-DSC-D is a reliable and easy-to-use and integrate IP core.

View Partner Website Right arrow Right arrow Partner Product Page Right arrow Right arrow Contact Now

Key Features

  • Full compliance with the VESA DSC 1.2b specification
  • Backwards compatible with VESA DSC 1.1
  • RGB and YCbCr color space formats
  • 8, 10, 12, 14 and 16 bits per color component dynamic range
  • Native support for 4:4:4, 4:2:2 and 4:2:0 sampling formats
  • Up to 16 slices per line
  • Scalable architecture with configurable number of internal, parallel decoding slice-engines - 3 pixel/clock/engine for 4:4:4, 6 pixel/clock/engine for 4:2:2/4:2:0 sampling formats
  • Operation without external memory - Very low internal memory requirements (a few image lines)
  • Ultra-low latency performance (sub-line latency)
  • CPU/GPU-less, complete and standalone implementation
Expand Close
Keyfeatures main image

Offering Brief

Offering Brief

Device Family Agilex® 3 FPGAs and SoC FPGAs C-Series, Agilex® 5 FPGAs and SoC FPGAs D-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs M-Series, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX SoC FPGA, Stratix® 10 AX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA, Stratix® 10 TX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License No
Design Examples Available No
Demo No
Compliance No
Latest Quartus Version Supported 24.3.1
Development Language VHDL

Pre-synthesized and verified Netlist for FPGA and SoC devices

Release Notes, Design Specification and Integration Manual documents

Bit Accurate Model (BAM) and test vector generation binaries, including sample scripts

Pre-compiled RTL simulation model and gate-level simulation netlist

Self-checking testbench environment sources, including sample BAM generated test cases

Sample Simulation and Place & Route scripts

Ordering Information

UHT-DSC-D

from Direct

Order Now

Market Segment and Sub-Segments

Broadcast-252x228.svg

Broadcast

View Sub-Segments

Broadcast

ProAV

Back to Market