partner-offering-banner.png

Scalable Ultra-High Throughput 8/10/12-bit JPEG Decoder

Alma Technologies S.A.

Select

The UHT-JPEG-D core from Alma Technologies is an ultra-high throughput 8-bit Baseline and 10/12-bit Extended hardware JPEG decoder, designed to provide all the power needed in modern image and video compression applications. The UHT-JPEG-D is a scalable decoder core and it is available for Altera FPGA and SoC based designs.

The UHT-JPEG-D accepts the standalone and standard compliant JPEG byte-stream generated by the matching Alma Technologies UHT-JPEG-E encoder IP, or other compatible JPEG byte-stream, and outputs the decoded data in raster scan format. It supports decoding of 4:4:4, 4:2:2, 4:2:0 and 4:0:0 (grayscale) image or video streams, in 8-, 10- or 12-bit per component sample depths. The UHT-JPEG-D can be implemented using only on-chip memory resources, while using off-chip memory too is also a supported option. Designed with a configurable architecture, the decoder scales to offer a decoding throughput from 1 up to 32 samples per clock cycle.

The UHT-JPEG-D core from Alma Technologies is an ultra-high throughput 8-bit Baseline and 10/12-bit Extended hardware JPEG decoder, designed to provide all the power needed in modern image and video compression applications. The UHT-JPEG-D is a scalable decoder core and it is available for Altera FPGA and SoC based designs.

The UHT-JPEG-D accepts the standalone and standard compliant JPEG byte-stream generated by the matching Alma Technologies UHT-JPEG-E encoder IP, or other compatible JPEG byte-stream, and outputs the decoded data in raster scan format. It supports decoding of 4:4:4, 4:2:2, 4:2:0 and 4:0:0 (grayscale) image or video streams, in 8-, 10- or 12-bit per component sample depths. The UHT-JPEG-D can be implemented using only on-chip memory resources, while using off-chip memory too is also a supported option. Designed with a configurable architecture, the decoder scales to offer a decoding throughput from 1 up to 32 samples per clock cycle.

The UHT-JPEG-D uses a single compressed data input interface and produces the raster scan decoded data through a single - multiple pixels - output interface. Its operation is completely standalone, without needing any host CPU or GPU power.

Key Features

  • Ultra-high throughput using scalable and transparent parallel processing
  • ITU T.81 compliance
  • 4:4:4, 4:2:2, 4:2:0 and 4:0:0 (grayscale) image or video data decoding
  • 8-, 10- and 12-bit per component sample depth
  • Single JPEG byte-stream input and single - multiple pixels - raster scan decoded output
  • Motion JPEG payload decoding
  • Up to 32 samples per clock cycle decoding
  • CPU-less, complete and standalone operation
Expand Close
Keyfeatures main image

Offering Brief

Offering Brief

Device Family Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST SoC FPGA, Arria® V SX SoC FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE SoC FPGA, Cyclone® V ST SoC FPGA, Cyclone® V SX SoC FPGA, Agilex® 3 FPGAs and SoC FPGAs C-Series, Agilex® 5 FPGAs and SoC FPGAs D-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs M-Series, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX SoC FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Stratix® 10 AX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA, Stratix® 10 TX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License No
Design Examples Available No
Demo No
Compliance No
Latest Quartus Version Supported 24.3.1
Development Language VHDL

Pre-synthesized and verified Netlist for FPGA and SoC devices

Release Notes, Design Specification and Integration Manual documents

Bit Accurate Model (BAM) and test vector generation binaries, including sample scripts

Pre-compiled RTL simulation model and gate-level simulation netlist

Self-checking testbench environment sources, including sample BAM generated test cases

Sample Simulation and Place & Route scripts

Ordering Information

Market Segment and Sub-Segments