TSN-EP-10G: 10G TSN Ethernet Endpoint Controller

Overview Key Features Offering Brief What's Included Ordering Information Documentation & Resources Markets

Computer Aided Software Technologies, Inc (dba CAST)

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The TSN-EP-10G implements a configurable controller meant to ease the implementation of endpoints for networks complying to the Time Sensitive Networking (TSN) standards. It integrates hardware stacks for timing synchronization (802.1AS-2020) and traffic shaping (802.1Qav and 802.1Qbv) and a low-latency Ethernet MAC. Enhanced reliability features can also be supported, using the optional hardware modules for FRER Frame Replication and Elimination for Reliability (802.1CB) and PSFP Per-Stream Filtering and Policing (802.1Qci).

The controller core is designed to enable high-precision timing synchronization and flexible yet accurate traffic scheduling. Requiring minimal software assistance for its initialization, it features extremely low and deterministic ingress and egress latencies and simplifies the development of time-aware applications. While operating autonomously, the TSN-EP-10G provides the system with timing information (timestamps, alarms, etc.) that is typically required for the operation of a TSN network endpoint device. Furthermore, it allows the system to define and tune in real time the traffic shaping parameters according to an application’s requirements.

The TSN-EP-10G uses standard AMBA® interfaces to ease integration. Its configuration and status registers are accessible via a 32-bit-wide APB bus, and packet data are input and output via 128-bit-wide AXI-Streaming buses. To further expedite and ease the implementation of customer applications, DMA engines providing access to the stream interfaces via a memory-mapped AXI4 master port, and software stacks supporting higher-layer protocols, such as 802.1Qcc, 802.1Qca and SNMP, are optionally available.

The TSN-EP is designed with industry best practices and is available in synthesizable RTL source code or as a targeted FPGA netlist. Deliverables provide everything required for a successful implementation, including sample scripts, an extensive testbench, and comprehensive documentation.

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Key Features

802.1AS-2020 FreeRTOS and Linux gPTP stack
Hardware-based 802.1Qav, 802.1Qbv
Optional 802.1Qci (hardware) and two software modules: 802.1Qcc, 802.1Qca
Low-Latency MAC
FreeRTOS Drivers, HAL, CLI
XGMII PHY interface
AXI-Stream interface
Optional Linux integration package

Offering Brief

Device Family	Agilex™ 3 FPGA C-Series, Agilex™ 5 FPGA D-Series, Agilex™ 5 FPGA E-Series, Agilex™ 7 FPGA F-Series, Agilex™ 7 FPGA I-Series, Agilex™ 7 FPGA M-Series, Agilex™ 9 FPGA Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX FPGA, Cyclone® 10 GX FPGA, Stratix® 10 AX FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX FPGA, Stratix® 10 TX FPGA, Stratix® IV GT FPGA, Stratix® IV GX FPGA, Stratix® V E FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status	Production
Integrated Testbench	Yes
Evaluation License	Yes
Design Examples Available	Yes
Demo	No
Compliance	No
Latest Quartus Version Supported	24.3.1
OS Support	FreeRTOS,Linux
Development Language	Encrypted Verilog, Verilog