LDPC for 5G NR (Silicon Proven IP for Altera Devices)

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Mobiveil Inc.

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Configurable 5G NR LDPC encoder/decoder IP compliant with 3GPP TS 38.212 (Rel-17), supporting Base Graphs 1 & 2, wide lifting sizes (2–384), early-termination, and runtime-configurable code length/rate for high-throughput, low-latency 5G designs. Technology-independent, system-validated LDPC core for 5G NR PDSCH/PUSCH that implements min-sum decoding with programmable internal/LLR widths, HARQ combining, per-block selectable CB length / code rate / base graph / max iterations, and early exit via concurrent parity checks. Deliverables include synthesizable parameterized Verilog, synthesis scripts, UVM testbench & regression, test-vector software, C++ bit-accurate model, and documentation. Throughput scales with iterations and parallelism (graphs provided at 400 MHz clk).

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Key Features

Full support of 5G NR specification (38.212 v17)
Support for all Base Graphs 1/2 codes
Additional Measurement Outputs (number of iterations, other) beyond the scope of 5G physical channel measurement specified in 38.215
Per-block modifiable code block length, code rate, base graph, and maximum number of iterations
Supports for lifting sizes from 2 to 384
Early termination based on syndrome check on each iteration and layer
Supports FPGA, ASIC Platforms
Testbench option

Offering Brief

Device Family	Agilex® 3 FPGAs and SoC FPGAs C-Series, Agilex® 5 FPGAs and SoC FPGAs D-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs M-Series, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX SoC FPGA, Stratix® 10 AX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA, Stratix® 10 TX FPGA
Offering Status	Production
Integrated Testbench	Yes
Evaluation License	Yes
Design Examples Available	No
Demo	No
Compliance	No
Latest Quartus Version Supported	24.3.1
Development Language	Encrypted Verilog, Verilog