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Cortex-A76 Software Development

HandsOn-Training

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Agilex™ 5 implements Armv8.2 architecture which has many benefits. The training covers all new architecture features, guide engineers how to utilize the new features and optimize performance, code density, power consumption, and debug. Extensive hands-on labs to practice all necessary aspects of the CPU.

Agilex™ 5 HPS gets significant uplift, versus the prior architectures with dual Cortex-A76 plus dual Cortex-A55 plus DynamIQ Shared Unit (DSU) that forms the upgraded MPU architecture.

Upgraded Application Processor Subsystem (APS). New Cache Coherency Unit (CCU), Generic Interrupt Controller (GIC), System Memory Management Unit (SMMU), and On-Chip RAM (OCRAM) that supports the new architecture. Cortex-A76 MPCore software development is a 4 days ARM official course. The course goes into great depth and provides all necessary know-how to develop software for systems based on Cortex-A76 processors.

The course introduces the ARMv8-A architectur...

Agilex™ 5 implements Armv8.2 architecture which has many benefits. The training covers all new architecture features, guide engineers how to utilize the new features and optimize performance, code density, power consumption, and debug. Extensive hands-on labs to practice all necessary aspects of the CPU.

Agilex™ 5 HPS gets significant uplift, versus the prior architectures with dual Cortex-A76 plus dual Cortex-A55 plus DynamIQ Shared Unit (DSU) that forms the upgraded MPU architecture.

Upgraded Application Processor Subsystem (APS). New Cache Coherency Unit (CCU), Generic Interrupt Controller (GIC), System Memory Management Unit (SMMU), and On-Chip RAM (OCRAM) that supports the new architecture. Cortex-A76 MPCore software development is a 4 days ARM official course. The course goes into great depth and provides all necessary know-how to develop software for systems based on Cortex-A76 processors.

The course introduces the ARMv8-A architecture, instruction set, and the new model to handle interrupts and exceptions. The course continues by covering the Cortex-A76 MPCore architecture based on DynamIQ technology, memory management unit, memory model, cache and branch prediction, cache coherency, processes synchronization, boot process, barriers, virtualization, Generic Interrupt Controller. TrustZone, debug and much more.

Key Features

  • Understand the advantages of DynamIQ technology.
  • Deploy efficient interrupt handling strategy with ARMv8-A exception model and GIC programming.
  • Be able to configure the MMU based on the ARMv8-A memory model. Work effeciently with the caches and branch prediction, as well as cache coherency between multi core.
  • Write drivers and use the Barriers instructions. Write efficient C/C++ code. Debug with invasive and non-invasive techniques.
  • Secure your product with TrustZone infrastructure. Become familiar with virtualization and its effect on the system.

Offering Brief

Offering Brief

Device Family Agilex® 5 FPGAs and SoC FPGAs D-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series
Offering Status Production
Prerequisites Embedded systems software design
Languages English
Target Audience embedded software engineers
Hands On Lab False

Arm official course book

Documentation & Resources

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