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Altera FPGA Designer Program

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Looking to train your employees to become FPGA designers? The Altera FPGA Designer Program was developed for such purpose. The course intention is to train computer and electronics engineers from scratch to a practical work level. The course goes into great depth, and touches upon every aspect of the VHDL standard and Altera FPGA design with directly connected to the topics needed in the industry today. The course combines 50% theory with 50% practical work in every meeting with Terasic DE0-CV evaluation board. The practical labs cover all the theory and also include practical digital design. The program provides extra labs/mini projects for homework between meetings.

We trained thousands of FPGA engineers during the years and that program developed from many years of experience and with Altera. This program brings an electrical engineer without any FPGA design experience to a working level in that field. The training combines digital design techniques, ...

Looking to train your employees to become FPGA designers? The Altera FPGA Designer Program was developed for such purpose. The course intention is to train computer and electronics engineers from scratch to a practical work level. The course goes into great depth, and touches upon every aspect of the VHDL standard and Altera FPGA design with directly connected to the topics needed in the industry today. The course combines 50% theory with 50% practical work in every meeting with Terasic DE0-CV evaluation board. The practical labs cover all the theory and also include practical digital design. The program provides extra labs/mini projects for homework between meetings.

We trained thousands of FPGA engineers during the years and that program developed from many years of experience and with Altera. This program brings an electrical engineer without any FPGA design experience to a working level in that field. The training combines digital design techniques, HDL language, simulation and synthesis, and FPGA design tools on a real hardware.

Key Features

  • Implement combinational and sequential processes and build hierarchy.
  • Understand coding style considerations for synthesis.
  • Write simple and complex test-benches. Configure and embed IPs in your design.
  • Identify and fix timing issues. Design pipeline circuits with an emphasis on latency and throughput.
  • Design a reliable multi-clock domains system with synchronization circuits.
  • Optimize the design with synthesis and Place & Route tools.
  • Debug your design on a real hardware.

Offering Brief

Offering Brief

Device Family Arria® 10 SX SoC FPGA, Cyclone® IV GX FPGA, Agilex® 5 FPGAs and SoC FPGAs E-Series, MAX® 10 FPGA, Cyclone® V SX SoC FPGA, Arria® V GZ FPGA, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, MAX® V CPLD, Agilex® 7 FPGAs and SoC FPGAs I-Series, Arria® V SX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 SX SoC FPGA, Agilex® 7 FPGAs and SoC FPGAs M-Series, Cyclone® V GT FPGA, Arria® 10 GT FPGA, Arria® V ST SoC FPGA, Arria® 10 GX FPGA, Stratix® 10 TX FPGA, Cyclone® V SE SoC FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Arria® V GX FPGA, Cyclone® V E FPGA, Agilex® 3 FPGAs and SoC FPGAs C-Series, Cyclone® V GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA, Cyclone® V ST SoC FPGA, Agilex® 5 FPGAs and SoC FPGAs D-Series, Stratix® 10 GX FPGA, Arria® V GT FPGA, Cyclone® 10 LP FPGA, Agilex® 7 FPGAs and SoC FPGAs F-Series, Cyclone® 10 GX FPGA, Stratix® 10 AX SoC FPGA, Cyclone® IV E FPGA, Stratix® III FPGA
Offering Status Production
Prerequisites Electrical engineering degree
Languages English
Target Audience Electrical engineers without or low FPGA experience
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