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UVM Fundamentals

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Developed for Marvell, now available for the FPGA market. Learn how to verify complex FPGA and SoC FPGA designs. Master all UVM fundamentals with extensive hands-on labs.

High-end FPGA designs such as Agilex™ 7 and Agilex™ 9 require intensive verification to decrease time to market. Universal Verification Methodology (UVM) is a standardized methodology for verifying digital designs and SoC. It is built on top of SV language and consists of set of standards, tools, and APIs for design verification. UVM helps companies develop modular, reusable, and scalable test benches that can be deployed across multiple projects. The training introduces the UVM and its structure, then covers the UVM library, reporting mechanism, factory, TLM, configuration database, phases, hierarchy, test and testbench top. Then the training covers how to generate stimulus with sequences and virtual sequences as well as using RAL. Extensive practical labs are integrated during the tra...

Developed for Marvell, now available for the FPGA market. Learn how to verify complex FPGA and SoC FPGA designs. Master all UVM fundamentals with extensive hands-on labs.

High-end FPGA designs such as Agilex™ 7 and Agilex™ 9 require intensive verification to decrease time to market. Universal Verification Methodology (UVM) is a standardized methodology for verifying digital designs and SoC. It is built on top of SV language and consists of set of standards, tools, and APIs for design verification. UVM helps companies develop modular, reusable, and scalable test benches that can be deployed across multiple projects. The training introduces the UVM and its structure, then covers the UVM library, reporting mechanism, factory, TLM, configuration database, phases, hierarchy, test and testbench top. Then the training covers how to generate stimulus with sequences and virtual sequences as well as using RAL. Extensive practical labs are integrated during the training to make sure that the participant understand the flow, structure and concept of each verification building block.

Key Features

  • Become familiar with UVM structure and UVM library basics.
  • Create objects, components and use the factory and factory overrides.
  • Analyze and debug the design with TLM elements and scoreboards.
  • Build hierarchical testbenches and configure various components.
  • Generate stimulus via virtual or physical sequences and run them.
  • Implement RAL and access it through frontdoor and backdoor.

Offering Brief

Offering Brief

Device Family Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, Stratix® 10 TX FPGA, Agilex® 5 FPGAs and SoC FPGAs D-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Stratix® 10 GX FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® 10 DX FPGA, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Stratix® 10 SX SoC FPGA, Agilex® 7 FPGAs and SoC FPGAs M-Series, Stratix® V GS FPGA, Stratix® V GX FPGA, Stratix® 10 AX SoC FPGA
Offering Status Production
Prerequisites FPGA design and verification
Languages English
Target Audience FPGA design and verification engineers
Hands On Lab False

Course book

VM with all tools, labs and solutions

Documentation & Resources

Market Segment and Sub-Segments