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Scalable Ultra-High Throughput Image and Video Scaler

Alma Technologies S.A.

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The UHT-SCALER core provides a video processing block which converts input video frames of one size and sampling format to output frames of a different size and/or sampling format. It supports scaling of 4:4:4, 4:2:2, 4:2:0 and 4:0:0 (grayscale) video streams with 8- up to 16-bit color depth, using the BILINEAR, BICUBIC, LANCZOS and EXPFILTER scaling methods. High quality de-Bayer support is also included. The UHT-SCALER is a standalone and high-performance image and video scaler core, designed for enabling high-quality and ultra-high throughput performance, even in low-end target silicon technologies. The UHT-SCALER is available for Altera FPGA and SoC based designs.

The core accepts the input image data in planar or interleaved scan order format and outputs the scaled image data in the same planar or interleaved format as the input. The UHT-SCALER is very easy to use and integrate in a system. It requires minimal host intervention as it only needs to b...

The UHT-SCALER core provides a video processing block which converts input video frames of one size and sampling format to output frames of a different size and/or sampling format. It supports scaling of 4:4:4, 4:2:2, 4:2:0 and 4:0:0 (grayscale) video streams with 8- up to 16-bit color depth, using the BILINEAR, BICUBIC, LANCZOS and EXPFILTER scaling methods. High quality de-Bayer support is also included. The UHT-SCALER is a standalone and high-performance image and video scaler core, designed for enabling high-quality and ultra-high throughput performance, even in low-end target silicon technologies. The UHT-SCALER is available for Altera FPGA and SoC based designs.

The core accepts the input image data in planar or interleaved scan order format and outputs the scaled image data in the same planar or interleaved format as the input. The UHT-SCALER is very easy to use and integrate in a system. It requires minimal host intervention as it only needs to be programmed once per video sequence. Once programmed, it can scale an arbitrary number of video frames without the need of any further intervention or assistance by the host system CPU.

Key Features

  • Programmable image dimensions from 8 x 8 up to 64k x 64k
  • Supports YCbCr/RGB 4:4:4, YCbCr 4:2:2, YCbCr 4:2:0 and single-color 4:0:0 video formats
  • High quality de-bayering when input is provided in any RGB Bayer format
  • 8 up to 16 bits per sample depth encoding
  • Support for bilinear, bicubic, lanczos and expfilter scaling algorithms
  • CPU-less, complete and standalone operation.
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Offering Brief

Offering Brief

Device Family Arria® II GX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST SoC FPGA, Arria® V SX SoC FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE SoC FPGA, Cyclone® V ST SoC FPGA, Cyclone® V SX SoC FPGA, Agilex® 3 FPGAs and SoC FPGAs C-Series, Agilex® 5 FPGAs and SoC FPGAs D-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs M-Series, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX SoC FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Stratix® 10 AX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA, Stratix® 10 TX FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License No
Design Examples Available No
Demo No
Compliance No
Latest Quartus Version Supported 24.3.1
Development Language VHDL

Clear-text RTL sources for ASIC designs, or pre-synthesized and verified Netlist for FPGA and SoC devices

Release Notes, Design Specification and Integration Manual documents

Bit Accurate Model (BAM) and test vector generation binaries, including sample scripts

Pre-compiled RTL simulation model and gate-level simulation netlist for the FPGA Netlist license

Self-checking testbench environment sources, including sample BAM generated test cases

Simulation and Place & Route scripts

Ordering Information

Market Segment and Sub-Segments