XJDeveloper & XJDeveloper Plus - IDE for PCB test development

Overview Key Features Offering Brief What's Included Ordering Information Documentation & Resources Markets

XJTAG

Member

XJDeveloper is an Integrated Development Environment for development and execution of circuit tests. Through its intuitive design flow, engineers have easy access to XJTAG’s market-leading test technology:

View Partner Website

Partner Product Page

Contact Now

Contact XJTAG

LeadSource

ASAP Account ID

Record Type Name

Key Features

Offering Brief

Device Family	Arria® II GX FPGA, Arria® V GT FPGA, Arria® V GX FPGA, Arria® V GZ FPGA, Arria® V ST SoC FPGA, Arria® V SX SoC FPGA, Cyclone® III FPGA, Cyclone® IV E FPGA, Cyclone® IV GX FPGA, Cyclone® V E FPGA, Cyclone® V GT FPGA, Cyclone® V GX FPGA, Cyclone® V SE SoC FPGA, Cyclone® V ST SoC FPGA, Cyclone® V SX SoC FPGA, Agilex® 3 FPGAs and SoC FPGAs C-Series, Agilex® 5 FPGAs and SoC FPGAs D-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs M-Series, Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX SoC FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, MAX® 10 FPGA, Stratix® 10 AX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA, Stratix® 10 TX FPGA, MAX® V CPLD, Stratix® III FPGA, Stratix® IV E FPGA, Stratix® IV GX FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status	Production
OS Support	Windows 11

Testing Connections - XJTAG’s Advanced Interconnection Test provides the core of the test coverage for your circuit. This allows you to test a higher percentage of a circuit than most other JTAG solutions, and is automatically generated from circuit data given during setup. Nets accessible through JTAG or other connections are checked for short- and open-circuit faults, including missing pull-up/pull-down resistors and resistive short-circuit errors. It also dynamically drives the logic devices in the circuit, giving test coverage to nets which are accessible only through logic devices.

XJEase Model Library - XJTAG checks the connectivity of non-JTAG devices by running tests against device models written in the XJEase language, normally from XJTAG’s built-in test library. These tests can respond to device behaviour and so can vary the tests performed based on the response to initial scans.

Device-Centric Tests - XJTAG’s library tests are device-centric – they are specific to the type of device being tested but not to the circuit they are placed in, or to the JTAG devices that are used to drive the nets on the PCB. Not only can tests easily be added to a project but they can be re-used in another project without modification wherever that type of device is used. Over time, this helps XJTAG to greatly reduce the engineering costs of test development. XJDeveloper provides a full range of test debugging capabilities and gives you access to the source code for every test provided in the XJTAG library. It is therefore possible to see the tests in operation and adapt them as required for new devices.

Fault Analysis - The main purpose of a JTAG-based test system is to detect faults in PCB assemblies, but the true value of this system is in its ability to accurately identify the cause of the faults. XJDeveloper can find and identify a wide range of faults. Information about the faults can be combined with imported Netlist and Schematic diagrams to graphically show the nets exhibiting faults. Nets can be highlighted on both the Schematic Diagram and the PCB layout, using XJDeveloper’s viewer tools. The Schematic Viewer and Layout Viewer are also accessible in XJRunner, XJTAG’s production test environment, and XJInvestigator, the advanced fault diagnosis/rework station. These powerful features, provided as standard, take fault analysis to a new level. Being able to see all of the points on a net where a short-circuit may have occurred due to a manufacturing defect, for example, can save valuable time in rework.

In-System Programming - In-System Programming (ISP) through a JTAG tool provides a simple way of configuring non-volatile memory during or after PCB assembly. XJDeveloper can be used to perform In-System Programming of flash and FPGA/CPLDs. JTAG can be used to configure programmable devices of any size, by serially shifting address, data and control information through the JTAG chain to the relevant device. This is perfect for programming smaller amounts of data such as MAC addresses or serial numbers into an EEPROM, but far too slow for programming large images in a production environment. The answer to this is hardware-accelerated programming.

Accelerated Programming - XJTAG has used its expertise in JTAG to offer industry-leading solutions to the challenge of delivering faster hardware-accelerated programming over a boundary scan interface. This typically involves the temporary reconfiguration of an FPGA on a board as an ‘in-system programmer’, allowing XJTAG to program large non-volatile flash memories, with the speed often being limited only by the device being programmed. XJTAG calls this solution XJFlash. It has been shown to result in programming cycle times that are 50 times faster than just using boundary scan test and in some cases, the programming times are even faster than a manufacturer’s published figures. XJTAG offers a range of acceleration options, including XJFlash for programming using FPGAs or CPLDs, and XJDirect, which programs using an on-board CPU or Microcontroller. Other applications may have more unusual requirements, and for such boards, XJTAG offers a consultancy service to develop bespoke solutions. Any programmable devices on a board can be used to deliver the desired results at high speed. Please contact us if you would like to know more.