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Random Access NVMe IP core (raNVMe-IP)

raNVMe-IP (Random Access NVMe IP) is specifically optimized for random access and low latency. It can achieve over 700K IOPS for random write access on high-performance NVMe™ SSDs without CPU intervention. This makes it ideal for applications like database search, which require frequent, high-speed access to NVMe SSDs.

RapidIO to AXI Bridge Controller (Silicon Proven IP for Altera Devices)

Mobiveil’s RIO-AXI Bridge provides a layered, configurable architecture connecting RapidIO to AXI-based systems. It includes high-speed DMA and streaming engines to meet demanding bandwidth needs. Technology-agnostic and highly integrable, it suits cost-sensitive, performance-driven designs in FPGAs and ASICs.

Real-Time JPEG Compression IP

Gidel’s real-time JPEG image compression (encoder) IP enables high-performance JPEG compression on FPGA. The compression IP is unique in its fast processing capacity, low latency, and compact silicon utilization. As a result of its compactness, the IP can be implemented on a small FPGA device to compress high-performance camera image streams or, alternatively, instantiated multiple times on a single larger FPGA device. The JPEG IP can be embedded seamlessly in Gidel's image acquisition systems, including the Gidel frame grabbers and compact edge computers. The compression supports high-end camera streaming, including 10+ GigE Vision, CoaXPress and Camera Link. Gidel's real-time compression IPs are particularly beneficial for high-bandwidth and high-resolution imaging application enabling increased recording time, reduces storage size, and reduced post recording data offload and compression time on host computer.

Reed Solomon II FPGA IP Core

The Reed Solomon II IP offers a fully parameterizable Reed Solomon encoder and decoder.

RS IP

The Reed-Solomon (RS) IP Core is a powerful and flexible Forward Error Correction (FEC) engine designed to enhance data integrity in digital communication systems. Leveraging the robust error-correcting capabilities of RS codes, this IP core ensures resilience against burst errors and improves overall system reliability across a wide range of applications including satellite communications, storage systems, digital broadcasting, and high-speed networking.

RTC Master (Real-Time Clock)

Full standalone hardware only solution of an RTC Master

RunX Low-Latency H.264 Video Encoder IP Core

Low-latency, hardware-optimized H.264/AVC video encoder IP core suitable for both FPGA and ASIC implementations in real-time embedded systems.

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S10PCIe-TS

The MPAC6500 (Hambledon) is a full-height, full-length PCIe Gen3 x16 FPGA packet-processing card with an Intel® Stratix® 10 FPGA and 4×100GBASE-LR4/SR4 QSFP28 interfaces.

SATA 3 Controller IP

Logic Fruit's SATA 3 Controller IP enables fast and efficient connectivity for storage devices, supporting high-speed data transfer. It works seamlessly with both newer and older SATA interfaces.