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Silicom FPGA SmartNIC N6010/6011 (N6001-PL/N6000-PL Arrow Creek)

The Silicom FPGA SmartNIC N6010/N6011 is a high-performance OEM hardware platform built on Altera’s Agilex™ AGFB014 FPGA with an embedded quad-core ARM Cortex-A53 HPS, designed to accelerate mobile 4G/5G baseband or distributed units via dual QSFP28/56 ports. Based on Intel/Altera N6000-PL.

SmartNIC HFT

The SmartNIC HFT Solution is a low-latency, FPGA/SoC-based Network Interface Card built for high-frequency trading. It accelerates trading functions in hardware with cut-through packet processing, custom protocol parsing, and kernel bypass—delivering near-zero latency and deterministic performance.

SmartNIC N3070X

The Napatech SmartNIC N3070X is a 400G PCIe Gen5 card featuring Agilex™ AGI041 FPGA, which supports hardened 100/200Gbps Ethernet and multiple PCIe 5.0 interfaces for high-speed data processing and offload capabilities.

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SoC FPGA Design

Accelerate your complex SoC FPGA Design with rsyocto. Bring your complex SoC FPGA designs to the next level with rsyocto's cutting-edge design services. By seamlessly integrating the FPGA, SoC, Desktop, and Cloud environments, we empower partners to innovate faster and smarter by linking all the different advantages tightly together.At rsyocto, we specialize exclusively in Altera SoC FPGAs, providing unmatched expertise in: FPGA design, real-time system design, ARM-based Hard Processor System (HPS) design, SoC FPGA interface design, Embedded Linux solutions, accelerator design and beyond. Our deep experience with Altera SoC FPGAs ensures a unique and optimized solution that combines FPGA and HPS partitions, Desktop software, Embedded Linux, and Cloud connectivity that ordinary FPGA, Linux, or cloud designers simply can't match.Flexible & Agile Partnerships: We don't just design hardware and software with a SoC — we build an environment. Starting with simple pencil sketches, rsyoct

SPMI-CTRL: MIPI SPMI Controller or Target

The SPMI-CTRL IP core implements the MIPI System Power Management Interface (SPMI) v2.0 protocol, enabling efficient and standardized communication between power management ICs (PMICs) and other components in complex SoCs. It can operate as either a controller or a target, making it flexible for a wide range of designs. The core autonomously manages critical protocol tasks such as command execution, ACK/NACK responses, arbitration, and address/data parity, minimizing host processor involvement and reducing system overhead. Its architecture is optimized for reliability and interoperability, ensuring robust power control and communication in mobile, automotive, and IoT devices. Supporting both single-master and multi-master configurations, the SPMI-CTRL offers scalability to meet diverse system requirements. Easy integration with standard system buses and configurability make it a practical, high-performance solution for developers implementing advanced power management networks.

ST 2022-8 Core

The Nextera-Adeas ST 2022-8 core enables SDI formatted signals over IP in a ST2110 environment.

ST 2059 PTP Core

The ST 2059 PTP core is an FPGA IP core that generates timing and clock signals according to the SMPTE ST 2059 standard defined by the Society of Motion Picture and Television Engineers. These deterministic timing signals can be used to time synchronize audio and video systems to a SMPTE ST2059 (PTP) grandmaster. The IP core provides broadcast and professional AV equipment the ability to support deterministic generation of timing (signals) for video and audio systems.

ST 2110 Core

Nextera-Adeas' industry-leading ST 2110 FPGA IP cores contain everything needed to IP-Enable your new or existing products quickly and easily. A full reference/demo design project is provided along with all of the drivers, daemons, system control software, and a Web GUI so customers can start with a working system and customize to their needs. Design services are also available to help accelerate time to market.

Starter Platform for OpenVINO™ Toolkit

Starter Platform for OpenVINO™ Toolkit is a PCIe based FPGA card with high performance and competitive cost. It's equipped with the largest Cyclone V GT(or GX)device at 301K LE and it supports PCIe Gen 2 x4(GX device will support PCIe Gen 1 x4). The board comes with 1GB DDR3, 64MB SDRAM, UART-to-USB interface, and extension headers such as GPIO and Arduino. This makes Starter Platform for OpenVINO™ Toolkit a re-configurable platform with adequate computing performance and low power consumption.