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SystemVerilog for Verification

This 5-days course designed for ASIC & FPGA verification engineers that would like to use the SystemVerilog and UVM to verify digital designs. SystemVerilog is a significant new enhancement to Verilog and includes major extensions into abstract design, test-bench, formal, and C-based APIs.

tCAM IP

In high-speed networking environments, efficient packet filtering is essential to maintain reliable and optimized data flow. Design Gateway’s tCAM IP core offers a high-performance, hardware-based solution that enables rapid packet classification using ternary matches—ideal for real-time network applications where speed and flexibility are critical. Unlike traditional memory, tCAM supports wildcard-based searches, making it especially effective for filtering complex rule sets in high-throughput scenarios. As software-based packet filtering struggles to meet the demands of growing data traffic, offloading these tasks to FPGA hardware delivers a significant performance advantage. By leveraging the power of Design Gateway’s tCAM IP core, users can dramatically reduce latency, increase throughput, and offload workloads from the CPU. This makes the solution ideal for applications such as high-speed routers, industrial networks, and edge computing systems. Our latest UDP Packet Filtering & S

TCC IP

Turbo Convolutional Codes (TCC) are an advanced class of Forward Error Correction (FEC) techniques that provide near-Shannon limit performance in digital communications. Widely adopted in 3G, 4G LTE, satellite, aerospace, and defense-grade communication systems, TCCs significantly enhance data integrity and transmission reliability in noisy environments.

TCPIP-100G: 100G TCP/UDP/IP Hardware Stack

The TCPIP-1G/10G core is a complete hardware TCP/IP stack that supports up to 32k sessions, DHCP, UDP with multicast, and offers configurable low-latency cut-through or reliable store-and-forward modes.

TCPIP-1G/10G: 1G/10G TCP/IP Hardware Stack

The TCPIP-1G/10G core is a complete TCP/IP hardware protocol stack, enabling systems to connect to IP networks and exchange TCP data without a host processor. Acting as server or client, it autonomously opens, maintains, and closes TCP connections. Network parameters are configured via control registers, while data is exchanged over streaming interfaces. The core is highly configurable: up to 32,768 simultaneous TCP sessions can be supported, or just one for minimal area designs. Options include a DHCP client, reassembly of out-of-order packets, and integration of a UDP hardware stack with IGMPv3 multicast. Users may select cut-through mode for ultra-low latency and minimal buffering, or store-and-forward mode for verified, in-order delivery. Available in RTL or FPGA netlist form, the core is rigorously verified and provided with testbench, synthesis/simulation scripts, and full documentation, making it ideal for applications ranging from servers to edge devices.

Terasic Cyclone® V SoC Development Kit with HSMC Connector (DE10-Standard)

The DE10-Standard Development Kit features an Altera SoC FPGA with dual-core ARM Cortex-A9 processors and programmable logic, delivering high performance, low power, and flexible reconfigurability for diverse design needs.

Terasic SoC System on Module Evaluation Kit

The Terasic SoC System on Module Evaluation Kit consists of the TSoM module and a TSoM-based board. The TSoM is a pocket-sized module powered by the latest Intel® Cyclone® V SoC FPGA. The board leverages the ARM dual-core Cortex-A9 CPU and 110K FPGA logic elements to deliver the lowest system cost and optimal power efficiency. The TSoM-based board expands the TSoM module with a variety of practical interfaces, enhancing overall equipment effectiveness (OEE) through IoT data and AI applications.

ThunderFjord Agilex™ 7 M-series FPGA SmartNIC

Silicom ThunderFjord board is high-performance programmable PCIe Gen5 x16 server adapter based on Agilex™ M-series FPGA (AGMF039 or AGMF032 option).Interfaces: Dual QSFPDD56 (2×400GE), supports multiple link combinations.Memory: Up to 32GB HBM2e with 2×2.6 Tbps bandwidth.Expansion: 2×ARC6-16 connectors (16×28Gbps) for PCIe, Ethernet, or interconnect options.Features: CXL 1.1/2.0, Quad-core ARM Cortex A53, flexible connectivity with breakout and flyover cables, direct card-to-card links.Applications: AI, machine learning, analytics, and other performance-intensive workloads.

Titan S10 SOM

The Titan S10 SOM is a compact, high-performance FPGA module based on the Altera Stratix® 10 SoC with 1.1M logic elements, dual DDR4 memory, high-speed transceivers, and flexible FMC/FMC+ interface options for compute-intensive embedded applications.