banner

Find Offerings

Switch to Partners

By Source
Offering Types
Region
Device Family
Market Segments
Program Level
Sort by
By Source
Offering Types
Region
Device Family
Market Segments
Program Level
Sort by

TLS 1.3 Client 10Gbps IP core (TLS10GC-IP)

TLS1.3 IP (Transport Layer Security IP) is a CPU-less, high-performance TLS v1.3 protocol engine for FPGA acceleration, requiring no CPU or external memory. It enables maximum Gigabit Ethernet throughput for secure data transmission over 1G/10G/25G/100G networks, making it ideal for Industrial IoT, automation, aerospace, and defense applications. Our demo showcases high-throughput HTTPS upload/download with a standard web server, achieved through pure hardware logic on FPGA.

TLS 1.3 Server 10Gbps IP core (TLS10GS-IP)

TLS1.3 IP (Transport Layer Security IP) is a CPU-less, high-performance TLS v1.3 protocol engine for FPGA acceleration, requiring no CPU or external memory. It enables maximum Gigabit Ethernet throughput for secure data transmission over 1G/10G/25G/100G networks, making it ideal for Industrial IoT, automation, aerospace, and defense applications. Our demo showcases high-throughput HTTPS upload/download with a standard web server, achieved through pure hardware logic on FPGA.

TOD Master (Time of Day, NMEA)

Full standalone hardware solution of a TOD Master

TOD Slave ( Time of Day, NMEA, UBX, TSIP, ESIP)

Full standalone hardware only solution of a TOD Slave

Tone Mapping Operator FPGA IP

The Tone Mapping Operator (TMO) FPGA IP corrects poorly exposed images and video to reveal invisible details.

TPC IP

Turbo Product Codes (TPC) are powerful Forward Error Correction (FEC) schemes that offer strong error-correcting capability with moderate complexity. TPCs are widely adopted in satellite communications, deep-space telemetry, aerospace systems, and military-grade networks, where low bit-error rates (BER) and high data integrity are essential under challenging noise conditions.

TR10a-HL Arria® 10 FPGA Development Kit

Terasic TR10a-HL Development Kit provides the ideal hardware solution for designs that demand high capacity and bandwidth memory interfacing, ultra-low latency communication, and power efficiency. With a full-height, 1/2-length form-factor package, the TR10a-HL is designed for the most demanding high-end applications, empowered with the top-of-the-line Altera Arria 10 GX, delivering the best system-level integration and flexibility in the industry.

TR10a-HL2 Arria® 10 FPGA Development Kit

Terasic’s TR10a-HL2 is designed to advance the agility, flexibility and speed and delivers blazing performance in cloud and data center applications.

Transparent Compression

Eideticom’s NoLoad Transparent Compression delivers high-performance inline data compression. Its NVMe-compliant interface ensures native driver support across all CPU platforms and operating systems, including Linux, FreeBSD, and Windows.