10GBASE-R PHY FPGA IP

Overview Key Features Offering Brief What's Included Ordering Information Documentation & Resources Markets

Altera

The 10GBASE-R PHY FPGA Intellectual Property (IP) core allows connectivity directly with any XFP or SFP+ optical module or with any external device with XFI and SFI interfaces. The PHY IP core can be used with either FPGA IP for 10G Ethernet MAC or with a customer-developed Ethernet MAC via a standard XGMII interface running at 156.25 Mbps.

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Key Features

PHY consisting of 10GBASE-R physical coding sublayer (PCS), 10.3125-Gbps physical medium attachment (PMA), and PHY management functions
Direct interface with 10GE MAC for a complete single-chip solution
PHY integrated into hard silicon in Intel® Arria® 10, Stratix® V, and Arria® V GZ FPGAs with 10.3125 Gbps serial transceivers
Soft 10GBASE-R PCS is also available in Stratix® IV GT and Arria® V (GT and ST) FPGAs
Direct 10.3125 Gbps serial connection for chip-to-chip, chip-to-optical module, chip-to-PHY device, and backplane applications
Local serial loop-back from transmitter to receiver at serial transceiver for testing, IEEE 1588 v2 option for high precision and accuracy time stamping.
Dynamic partial reconfigurable I/O (DPRIO) support in serial transceivers to adapt to various 10GBASE-R channel characteristics and devices in systems during operation
Implementing the Ethernet standard 10GBASE-R PHY functions: 64b/66b encoding or descrambling/descrambling, receiver rate matching for clock frequency compensation, 66b/16b gear-boxing, and data serialization or deserialization to and from 10.3125 Gbps line
Receiver-link fault status detection

Offering Brief

Device Family	Arria® V ST SoC FPGA, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX SoC FPGA, Cyclone® 10 GX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA, Stratix® 10 TX FPGA, Stratix® V GX FPGA
Offering Status	Production
Integrated Testbench	Yes
Evaluation License	Yes
Design Examples Available	Yes
Demo	Yes
Compliance	No
Development Language	Encrypted Verilog