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10GBASE-R PHY FPGA IP

Altera

The 10GBASE-R PHY FPGA Intellectual Property (IP) core can be used with either Altera FPGA IP for 10G Ethernet MAC or with a customer-developed Ethernet MAC via a standard XGMII interface running at 156.25 Mbps. The 10GBASE-R PHY FPGA Intellectual Property (IP) core allows connectivity directly with any XFP or SFP+ optical module or with any external device with XFI and SFI interfaces.

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Key Features

  • PHY consisting of 10GBASE-R physical coding sublayer (PCS), 10.3125-Gbps physical medium attachment (PMA), and PHY management functions; Direct interface with 10GE MAC for a complete single-chip solution
  • PHY integrated into hard silicon in Arria 10, Stratix V, and Arria V GZ FPGAs with 10.3125 Gbps serial transceivers
  • Soft 10GBASE-R PCS is also available in Stratix IV GT and Arria V (GT and ST) FPGAs; Direct 10.3125 Gbps serial connection for chip-to-chip, chip-to-optical module, chip-to-PHY device, and backplane applications
  • Dynamic partial reconfigurable I/O (DPRIO) support in serial transceivers to adapt to various 10GBASE-R channel characteristics and devices in systems during operation
  • Implementing the Ethernet standard 10GBASE-R PHY functions: 64b/66b encoding or decoding, scrambling/descrambling, receiver rate matching for clock frequency compensation, 66b/16b gear-boxing, and data serialization or deserialization to and from 10.3125G
  • Receiver-link fault status detection; Local serial loop-back from transmitter to receiver at serial transceiver for testing
  • IEEE 1588v2 option for high precision and accuracy time stamping
  • High-performance internal system interfaces
  • Avalon Streaming (Avalon-ST) single data rate (SDR) XGMII, 72 bits at 156.25 Mbps for data transfer
  • Avalon Memory-Mapped (Avalon-MM) 32 bits for management; IEEE 802.3 10GbE standard compliant, clauses 46, 49, and 51
  • Passed University of New Hampshire Interoperability Lab (UNH-IOL) 10 Gbps Ethernet MAC and PCS validation tests
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Offering Brief

Offering Brief

Device Family Arria® V GT FPGA, Arria® V GZ FPGA, Arria® V ST SoC FPGA, Stratix® V GS FPGA, Stratix® V GX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Demo No
Compliance No
Development Language Encrypted Verilog

Encrypted Verilog source file

Simulation models

Documentation: User Guide, Release Information

Ordering Information

IP-10GMRPHY (Arria 10 and Cyclone 10); IP-10GBASERPCS (Cyclone V); IP-10GETHMAC (10-Gbps Ethernet MA

from Digikey

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IP-10GMRPHY (Arria 10 and Cyclone 10); IP-10GBASERPCS (Cyclone V); IP-10GETHMAC (10-Gbps Ethernet MA

from Mouser

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IP-10GMRPHY (Arria 10 and Cyclone 10); IP-10GBASERPCS (Cyclone V); IP-10GETHMAC (10-Gbps Ethernet MA

from Mouser

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IP-10GMRPHY (Arria 10 and Cyclone 10); IP-10GBASERPCS (Cyclone V); IP-10GETHMAC (10-Gbps Ethernet MA

from Mouser

Order Now

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