Symmetric Cryptographic Accelerator Hard IP

Overview Key Features Offering Brief What's Included Ordering Information Documentation & Resources Markets

Altera

The Symmetric Cryptographic Accelerator Hard IP is a 200 Gbps hard IP core implementing AES or SM4 encryption and decryption. Typically, the AES and SM4 standards are used to protect the confidentiality of network data in 5G, data center, medical, test and video, but can be used to secure any high-speed data in transit. In fact, this hard IP is called by Altera's MACsec IP solution as a hardened accelerator, but can be used in any application requiring these encryption standards. In addition, the XTS profile can be used in data storage applications.

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Key Features

200 Gbps bandwidth highly configurable core, 100 Gbps full-duplex
Hard IP core with low LE count, configurable soft IP wrapper
Supports AES-GCM Mode, with 128bit or 256bit key sizes and meets NIST 800-38D
Supports AES-XTS Mode, with 128bit or 256bit key sizes and meets NIST 800-38E
Supports SM4 Mode, with 128bit key size meeting OSCCA GB/T 32907-2016
Hard IP additionally supports AES-CTR and AES-BulkECB Modes
Default support for MACsec, IPsec, generic GCM, generic XTS, and SM4 profiles
Supports interleaved profiles
Optimized for MACsec and IPsec
Can be used for DTLS, TLS1.3, QUIC, secure computing, and storage device encryption

Offering Brief

Device Family	Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series
Offering Status	Production
Integrated Testbench	Yes
Evaluation License	No
Design Examples Available	Yes
Demo	No
Compliance	No
Development Language	Verilog, VHDL