partner-offering-banner.png

Tone Mapping Operator FPGA IP

Altera

The Altera Tone Mapping Operator FPGA IP core enables real-time conversion of high dynamic range (HDR) video to standard dynamic range (SDR), preserving visual detail and contrast for display compatibility. Designed for applications like broadcast, automotive, and surveillance, it performs tone mapping in hardware to reduce latency and offload processing from general-purpose processors. Optimized for Altera FPGA platforms, the core integrates easily into image processing pipelines and supports configurable parameters for flexible deployment in embedded and edge systems.

Contact Now

Key Features

  • Multi-tile local image statistics analysis
  • Support for 8, 10 and 12 bit per color component
  • Support up to 4 pixels in parallel (PIP) per clock processing
  • Low subframe latency (~ 100 clock cycles)
  • Support resolutions up to 4K at 60 FPS on Cyclone® 10 FPGAs, Arria® 10 FPGAs, Stratix® 10 FPGAs, and Agilex® 5 FPGA E-Series
  • Support resolutions up to 8K at 60 FPS on Agilex® 7 FPGAs and on Agilex® 5 FPGA D-Series
  • AXI4-Stream video I/O interface
  • AXI4-Stream ↔ Avalon® streaming interface protocol converters
  • Avalon® memory-mapped CPU control and memory interfaces
  • Low resource utilization for edge applications
Expand Close
Keyfeatures main image

Offering Brief

Offering Brief

Device Family Agilex® 3 FPGAs and SoC FPGAs C-Series, Agilex® 5 FPGAs and SoC FPGAs D-Series, Agilex® 5 FPGAs and SoC FPGAs E-Series, Agilex® 7 FPGAs and SoC FPGAs F-Series, Agilex® 7 FPGAs and SoC FPGAs I-Series, Agilex® 7 FPGAs and SoC FPGAs M-Series, Arria® 10 GT FPGA, Arria® 10 GX FPGA, Arria® 10 SX SoC FPGA, Cyclone® 10 GX FPGA, Cyclone® 10 LP FPGA, Stratix® 10 AX SoC FPGA, Stratix® 10 DX FPGA, Stratix® 10 GX FPGA, Stratix® 10 SX SoC FPGA, Stratix® 10 TX FPGA
Offering Status Production
Integrated Testbench Yes
Evaluation License Yes
Design Examples Available Yes
Demo No
Compliance No
Development Language Encrypted Verilog, Encrypted VHDL

Encrypted Verilog source code

Design Example

Simulation Models

IP Evaluation Mode

Documentation: IP User Guide, IP Release Notes

Ordering Information

IP-OM-TMO

from Digikey

Order Now

IP-OM-TMO

from Mouser

Order Now

Market Segment and Sub-Segments

Broadcast-252x228.svg

Broadcast

View Sub-Segments

Broadcast

Broadcast Studio

Back to Market
Robotics-252x228.svg

Industrial

View Sub-Segments

Industrial

Vision

Back to Market
Medical-Video-and-Vision-252x228.png

Medical

View Sub-Segments

Medical

Imaging

Non-Imaging Patient Devices

Other Medical

Back to Market
Software-Defined-Vehicle-252x228.svg

Transportation

View Sub-Segments

Transportation

Automotive (Passenger Vehicles)

Back to Market